TCAN1042H: Question Regarding TIDA-01487

Hi Michael,

Thank you for your quick reply.

Michael Ikwuyum said:

(1) This seems to show the delay from one end of the bus to the other I.e., from one end's TXD input delay to the other end of the bus as shown below to help account for the added delay from all other devices from U6 to U7. 

I.e, the measurement points used for Figures 10 and 11 should be for TP3 (Channel 1) and U7 pin 7 (Channel 2) as stated in the design guide, where these points were used to characterize the delay-line behavior. Internal nodes such as TX1 (U3A pin 1) and U5A pin 7 can also be useful for debugging the delay circuit implementation, but they do not seem to be for the measurement points used for the published waveforms.

The customer confirmed this description and confusing.

According to 2.4.3 CAN Bus Arbitration Logic,

There is 210ns delay in the delay line logic  

The customer think about there some ICs and propagation delay to the U7-7pin,  

SN74LV32A x2 3.6nstypx2 

ISO7721 11nstyp

TCAN1042H 55nstyp

Total 73.2ns

However, the propagation delay on Figure 10 and Figure 11 are not added these propagation delay

This is the reason why the the customer think the measurement point is different.

Could you please clarify this?

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I appreciate your great help and cooperation.

Best regards,

Shinichi 

Hi Thomas Mauer (5601), 

I see you have clarified concerns on the reference design in the past.

Are you the author or do you know of another contact who could help double confirm customer's concerns? Thanks.

Best Regards,

Michael.

The important timing path for the delay-line logic is the round-trip propagation path through the repeater, not only the propagation delay of one individual device.
When the left CAN bus becomes dominant first, this dominant state is detected at TP6 / RX1. The arbitration logic then forwards this state to the opposite side through the path:

TP6 / RX1
→ arbitration logic
→ TP4 / TX2_
→ ISO7721
→ TXD of the right-side TCAN1042H
→ right CAN bus becomes dominant
→ RXD loopback of the right-side TCAN1042H
→ TP2 / RX2
→ ISO7721
→ TP1 / RX2_

This is the relevant round-trip path because the opposite-side RXD signal returns to the arbitration logic at TP1. The arbitration logic uses this returned signal to decide whether the path from TP1 to TP3 must remain blocked.

If the original left-side bus now releases from dominant to recessive, this recessive transition is first seen at TP6. However, the same recessive information also needs time to propagate through the opposite-side transceiver path and return to TP1. Until that returned signal has also become recessive, the arbitration logic must keep the path from TP1 to TP3 blocked. Otherwise, the still-dominant returned signal at TP1 could be forwarded back to TP3 and drive the left-side CAN transceiver dominant again. This could unintentionally hold the original left bus dominant even though the original transmitter has already released it.

Therefore, the delay-line logic intentionally delays the release of the blocked path. The delay must be longer than the round-trip propagation delay from TP6 to TP1, so that the recessive state has fully propagated through the opposite side and returned to the arbitration logic before the path is opened again.

Based on the design guide measurements, the delay from TP4 to TP1 was measured as approximately 108.5 ns. This includes the ISO7721 forward path, the right-side TCAN1042H loopback path, and the ISO7721 return path.

The additional logic delay from TP6 to TP4 is mainly the arbitration-logic path. Using two SN74LV32A gate delays gives approximately:
TP6 → TP4 ≈ 2 × 3.6 ns = 7.2 ns typical

Therefore, the expected round-trip delay is approximately:
TP6 → TP1 ≈ TP6 → TP4 + TP4 → TP1
TP6 → TP1 ≈ 7.2 ns + 108.5 ns
TP6 → TP1 ≈ 115.7 ns typical

So the relevant round-trip delay is approximately 116 ns typical.

The nominal 210 ns delay-line value was therefore selected with margin relative to this round-trip delay. It ensures that the blocked feedback path is not released too early during the dominant-to-recessive transition.

The measured delay-line value in the design guide is approximately 228 ns, which gives additional margin:
228 ns - 116 ns ≈ 112 ns margin

This also explains why the delay-line measurement itself should not be interpreted as including all device propagation delays from the complete repeater path. The delay-line circuit provides the intentional waiting time, while the round-trip path is the propagation delay that this waiting time must cover.

Regards,
Thomas