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66AK2L06: TI 66AK2L06 Soc to external PHY TI DP83867CSRGZ termination problem/question

Iiro Hietanen
Prodigy 10 points

Part Number: 66AK2L06

Sorry about the lengthy explanation, I have a bad habit of going deep into details..... so bear with me.

We have a SGMII-to-copper arrangement where TI 66AK2L06 Soc talks with an external PHY TI DP83867CSRGZ according to the attached, simplified diagramme.  I am showing here only the relavant part of the interconnection, since our tests seem to pinpoint a problem here. Pins/balls and pin names are shown.

 

image.png

We are using auto-negotiation between the two. We have a 4-wire arrangement where clock and data recovery are performed in the MAC and in the PHY, so no additional differential pair is required for clocking the SGMII data.

The questions relate to possible external terminations needed here.

 

Question 1, PHY end termination:

DP83867CSRGZ data sheet says: " PHY has inbuilt 100ohm differential termination at receive and transmit pins of SGMII." So we assume no external termination components are need at the PHY DP83867CSRGZ end here ? Please, confirm this.

 

Question 2: SoC RX input termination:

Then, for the Soc end, we do not seem to find a good enough explanation for the SGMII termination arrangement needs. 66AK2L06 datasheet has 300 pages but not enough solid information about SGMII terminations, as far as I am able to find.

In this document: "KeyStone II Architecture, Serializer/Deserializer (SerDes), User's Guide",  chapter 12 states:

"The SGMII specification calls for low-voltage differential signaling (LVDS), so additional terminations may be required. The need for terminations is dependent on the internal terminations in the link partner device."

Chapter 15 of same document is called "SerDes Receiver Calibration". It shows a diagramme with 50ohm resistors drawn from RX+ and RX- inputs to ground. It also says "RX termination is automatically calibrated on startup. The target differential impedance is set by loading
the SerDes configuration file provided by TI as part of the MCSDK. "

So, are these real physical termination resistors that exist there, so no external termination resistors are needed ? Or "Termination calibration" means that the 66AK2L06 internally adjusts the termination resistance based on a target input impedance value set using a  MCSDK or SDK package ? If yes, could you please provide more guidance on how this impedance setting is changed ?

 

Question 3: SoC TX output wires

Then, for Soc TX, question is more or less the same as in the case of RX. Chapter 14 or the document mentioned above discusses "TX Driver Output Swing and Slew " and "TX Driver Equalization " but termination requirements remain unclear.

Related drawing again uses term "Termination calibration". So same question here:

Are external termination resistors needed ? Or "Termination calibration" means that the 66AK2L06 internally adjust the termination resistance, also for TX, based on a target input impedance value set using a  MCSDK or SDK package ?

 

Question 4: What is "VDDALH SerDes termination supply" where nominal value is 0.85V ? How is this voltage used in relation to termination ? This is mentioned in 66AK2L06 datasheet (table 10.2 Recommended Operating Conditions)

 

Expert help on these would highly appreciated.

 

Best regards, Iiro H