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LSF0108: Query regarding the VIH,VIL, VOH and VOL of LSF0108DGSR

RAJ PANDA
Prodigy 10 points

Part Number: LSF0108

Dear Sir,

 We are planning to use the voltage level translator LSF0108DGSR in our design. Our use case is VrefA=1.2V and VrefB=3.3V. We wanted to know the VIH,VIL, VOH and VOL levels for both side. We went through the datasheet, did not able to find it. Can someone please guide us regarding this ?

Thanks & regards

Raj Kishore

 

  • 0
    TI__Intellectual 895 points

    Hi Raj,

    The VIH, VIL, VOH and VOL values are not specified for the LSF0108 data I/O pins because the LSF0108 is a passive FET-switch based voltage translator, not a buffered translator with defined input thresholds or output drive levels.

    For LSF0108, the logic thresholds are determined by the devices connected to each side of the translator.

    The high level on each side is set by the external pull-up voltage. In your case, the A side high level will be approximately 1.2 V and the B side high level will be approximately 3.3 V.

    When one side drives low, the pass FET conducts and pulls the opposite side low. The translated low level will be approximately the driving device VOL plus the voltage drop across the pass FET, which depends on the pull-up current and the on-resistance of the switch. Therefore, the pull-up resistor value should be selected to ensure that the translated VOL remains below the VIL(max) of the receiving device, while also meeting the required rise-time specification.

    Thanks.

  • 0
    Prodigy 10 points

    Hi Brian,

     thank you for the details. I went through the up translation video and understood that Vbias = VrefA+Vth; and the Vth =0.8V.  Also, understood that when VrefA side driver drives high and the signal voltage becomes same as VrefA , at that time internal FET turns off and next up translation from VefA to VrefB use to be taken care by VrefB side pull up Res. Please correct me if my understanding is wrong in any place.

    In our design , the VrefA side driver is a Xilinx FPGA and its LVCMOS12 IO level signal has the VIHmin=0.8V. Please kindly confirm if in worst case FPGA drives 0.8V considering as logic High , will the translator be able to convert the signal level to 3V3 level ?

    Thanks 

    Raj

  • 0 in reply to RAJ PANDA
    Guru 325980 points

    For the FPGA'a output signal, you would have to look at VOH, not VIH. And the actual output current is zero, so the actual output voltage will be 1.2 V. This will work.

  • 0 in reply to Clemens Ladisch
    Prodigy 10 points

    Hi Clemens,

     Sorry ,it was a typo from my side. my intension was VOH. But i did not get your answer " And the actual output current is zero, so the actual output voltage will be 1.2 V. This will work." . Can you please elaborate a little bit ?

    Thanks 

    Raj

  • 0 in reply to RAJ PANDA
    TI__Guru 60151 points

    Hi RAJ,

    I believe Clemens is referring the output of the LSF driving into the input stage of your downstream device via the external pullups to a high input impedance, or near zero output current, so the VOH will be very close to VCC.

    Regards,

    Jack