LMH1208: HOST_EQ0=H behavior, Reg0x3F[1], and OUT_CTRL-equivalent register state

Diego Shinji Kawaguchi

Part Number: LMH1208

Hello TI team,

I would like to ask a focused follow-up question regarding LMH1208 HOST_EQ0, Reg0x3F[1], and production register monitoring.

In my previous E2E question, TI confirmed that, for LMH1208, Reg0x3F[1]=1 is needed to override the IN0 EQ pin-control path when using register-controlled manual EQ.
LMH1208: LMH1208:Does manual EQ (Reg 0x2D/0x03) require setting Reg 0x3F[1] to takDoes manual EQ (Reg 0x2D/0x03) require setting Reg 0x3F[1] to take effect on SDI_OUT1? - Interface forum - Interface - TI E2E support forums

After additional measurements, we found that this issue appears to be specific to HOST_EQ0=H.

According to the LMH1208 datasheet, both HOST_EQ0=H and HOST_EQ0=F are documented as:

All Rates: AM0 Manual Mode, EQ = 0x00

However, our measurement result was:

HOST_EQ0=F, pin control only:
  waveform is equivalent to register-controlled manual EQ with Reg0x03=0x00

HOST_EQ0=H, pin control only:
  waveform is different from HOST_EQ0=F

HOST_EQ0=H + register-controlled manual EQ:
  Reg0x3F[1] = 1
  Reg0x2D[3] = 1
  Reg0x03    = 0x00
  waveform becomes equivalent to HOST_EQ0=F

Therefore, HOST_EQ0=F appears to behave as the documented EQ=0x00 state, even without setting Reg0x3F[1].

On the other hand, HOST_EQ0=H does not appear to behave the same as HOST_EQ0=F, even though both are documented as EQ=0x00.

We also tried changing the manual EQ value through Reg0x03, but we could not reproduce the slower waveform observed with HOST_EQ0=H pin control only.

One possible explanation we are considering is that, when HOST_EQ0=H is used, LMH1208 may retain some LMH1228-derived CDR-bypass-path-related condition. In such a condition, pre-emphasis or output conditioning may not be applied in the same way as in the normal-operation state. We are not assuming this is correct, but this is one possible explanation for why HOST_EQ0=H behaves differently from both HOST_EQ0=F and register-controlled Reg0x03=0x00.

My understanding is:

Reg0x3F[1]
  overrides IN0 EQ boost pin control.

Reg0x3F[3]
  is the OUT_CTRL pin override in LMH1228.

Reg0x1C[3:2]
  is used with the OUT_CTRL override in LMH1228.

Since LMH1208 has no physical OUT_CTRL pin, I would like to clarify how the OUT_CTRL-related behavior is represented internally in LMH1208.

My questions are:

Q1.
For LMH1208, is the following understanding correct?

HOST_EQ0=F pin-control state
≈ Reg0x3F[1]=1 + Reg0x2D[3]=1 + Reg0x03=0x00 register-control state

HOST_EQ0=H pin-control state
≠ HOST_EQ0=F pin-control state

If this is not correct, could you clarify why HOST_EQ0=H produced a different waveform from both HOST_EQ0=F and register-controlled Reg0x03=0x00?

Q2.
When Reg0x3F[1]=0, the LMH1228-derived description says that IN0 EQ boost bypass behavior is controlled by OUT_CTRL pin behavior.

For LMH1208, there is no physical OUT_CTRL pin. In that case, what is used as the OUT_CTRL behavior?

Is it:

A. hardwired internally to a fixed default state,
B. stored in a register-accessible field,
C. inherited from an LMH1228-derived Reserved/internal register state,
D. not applicable to LMH1208?

If it is B or C, please specify the register page, address, and bit field.

Q3.
For LMH1208, when Reg0x3F[3]=0, what is used as the OUT_CTRL state?

Since LMH1208 has no physical OUT_CTRL pin, does Reg0x3F[3]=0 refer to an internal fixed state, or to some register-accessible OUT_CTRL-equivalent state?

If it refers to a register-accessible state, which register field should be monitored?

Q4.
If Reg0x3F[1]=1 resolves the IN0 EQ behavior, but does not cover the entire OUT_CTRL-related behavior, are there any additional LMH1208 register bits that can affect the SDI_OUT1 waveform and should be monitored for production?

In particular, should any of the following LMH1228-derived fields or Reserved bits be monitored?

Reg0x3F[3]
Reg0x1C[3:2]
Reg0x09[5]
Reg0x1C[7:6]
Reg0x1E[7:5]
any other Reserved bit inherited from LMH1228

If none of these additional fields are relevant for LMH1208, could TI explicitly confirm that only the following fields need to be monitored to guarantee the intended register-controlled IN0 manual EQ=0x00 behavior?

Reg0x3F[1]
Reg0x2D[3]
Reg0x03[7:0]

My objective is to define a production register monitoring list so that any 1-bit change that can affect the SDI_OUT1 waveform is detected and corrected.

Best regards,
Diego

24 days ago

0 David (ASIC) Liu 24 days ago

TI__Guru**** 189451 points

Hi Kawaguchi-san,

With the HOST_EQ0 pin is also used to set OUT0 VOD and de-emphasis values,

Can you please manually set bit 5 and bit [2:0 of LMH1208 Driver Register 0x30 to manually set the VOD
Manually set bit 6 and bit [2:0] of LMH1208 Driver Register 0x31 to manually set the de-emphasis

If you manually control the OUT0 VOD and De-emphasis, do you still see a waveform difference between HOST_EQ0 = H and F with the EQ manual override procedure?

Thanks

David

0 Diego Shinji Kawaguchi 20 days ago in reply to David (ASIC) Liu

Prodigy 180 points

Hi David,

Apologies for the delayed response, and thank you for your suggestion.

I was not able to arrange a measurement instrument with sufficient bandwidth for 12G-SDI. Since video is not displayed with the initial HOST_EQ0 = H condition, while video is displayed with HOST_EQ0 = F, I used the presence or absence of video as a functional indicator.

One clarification regarding my setup is that only SDI_OUT1+ is used as the video output. OUT0+/- is not connected.

With HOST_EQ0 = H, applying the following EQ manual override procedure restored the video:

Reg0x3F = 0x03
Reg0x2D = 0x08
Reg0x03 = 0x00

I then applied the OUT0 settings you suggested:

Reg0x30 = 0x2A
Reg0x31 = 0x41

The readback values were correct, and the video remained displayed. However, because OUT0+/- is not used in my circuit, these registers do not directly control the SDI_OUT1+ output being observed.

As an additional check, I started again from the initial HOST_EQ0 = H no-video condition without applying the EQ manual override. Setting Reg0x30 = 0x2A and Reg0x31 = 0x41 alone did not recover the video.

I also programmed the SDI_OUT1 pre-emphasis register directly:

Reg0x62 = 0xD0: register control using the original pre-emphasis code
Reg0x62 = 0xF0: register control using the maximum pre-emphasis code

Both values were read back correctly, but neither setting recovered the video.

Regarding your question, I could not directly determine whether the electrical waveform difference between HOST_EQ0 = H and F still remains. With HOST_EQ0 = H, the video remained absent after programming both the original and maximum SDI_OUT1 pre-emphasis codes, whereas HOST_EQ0 = F produces valid video.

Therefore, at least functionally, this procedure did not reproduce the HOST_EQ0 = F behavior while HOST_EQ0 was set to H. However, because I could only confirm the register readback and could not measure the SDI_OUT1 waveform, I cannot verify that the intended manual pre-emphasis level was actually applied at the analog output.

Thanks,

Kawaguchi

0 David (ASIC) Liu 20 days ago in reply to Diego Shinji Kawaguchi

TI__Guru**** 189451 points

Kawaguchi-san

My apology as I thought you are using OUT0 output. Let me take a look at your latest response and I will provide my response.

Thanks

David

0 David (ASIC) Liu 17 days ago in reply to David (ASIC) Liu

TI__Guru**** 189451 points

Kawaguchi-san

With HOST_EQ0 = H, applying the following EQ manual override procedure restored the video:

Reg0x3F = 0x03
Reg0x2D = 0x08
Reg0x03 = 0x00

Are you able to restore the video with Reg0x3F = 0x02?

For the two conditions below

HOST_EQ0=F, pin control only:
  waveform is equivalent to register-controlled manual EQ with Reg0x03=0x00

HOST_EQ0=H, pin control only:
  waveform is different from HOST_EQ0=F

1. Can you read out Driver Register Page register 0x25?
2. With HOST_EQ0 = H, what is the current input data rate and input trace length you are using? If you change the data rate to 1.5G or 270M, do you see a difference? 

Thanks
David