TCAN4550-Q1: Crystal Oscillator Spec

Hello Han,

The TCAN4550-Q1 has two supported clock modes through the OSC1 and OSC2 pins. 

When used with a crystal, the OSC1 pin is the "Output" of the tranconductance amplifier that sources current to the crystal, and the OSC2 pin is the "Input" to the feedback loop of the amplifier and the OSC2 waveform is converted into a square wave clock and passed to the digital core and MCAN circuits.

There is a weak current source that "Outputs" a 1uA current on the OSC2 pin and a voltage comparator is used to measure the voltage on the OSC2 pin to determine if it is connected to GND and has a "low voltage" less than approximately 100mV or if it has a higher voltage.  If the OSC2 pin is not connected to GND, the voltage will be high and the device will operate in Crystal Mode, but if the OSC2 pin is connected to GND, the voltage will be low and the device will disable the transconductance amplifier and operate in single-ended mode. 

The threshold of this detection comparator on the OSC2 pin is typically 100mV, but it could vary between 90mV and 150mV depending on manufacturing process, voltage, and temperature conditions and so it is important to maintain the OSC2 pin voltage above 150mV at all times when using a crystal to avoid the risk of the device switching to single-ended clock mode which may cause SPI and CAN communication errors.

The TCAN4550-Q1 also has an Automatic Gain Control (AGC) and Peak Detection (PD) circuit that will monitor the peak-to-peak and common mode voltage on the OSC1 pin and adjust the amplifier current in order to maintain an approximate 1Vpp oscillation amplitude.  There is a minimum level of current that must always be output from the amplifier so if the amplitude exceeds 1Vpp when the AGC is at the minimum output level, the device will not be able to properly regulate the current and reduce the amplitude to a safe 1Vpp level and a change to the external load (capacitors, series dampening resistors, etc.) will be required to increase the load and allow the clock circuit to operate within the min/max limits.

Your waveform shows a 1.13Vpp and min voltage of 144mV which tells me that the device is likely operating outside of the AGC regulation region.  The board's parasitic capacitance makes up a portion of the total capacitive load (Cload) on the crystal and unlike ceramic capacitors, it is not very stable across temperature and will likely decrease with increasing temperature and will change the Cload on the crystal further decreasing the load on the amplifier and increases the oscillation amplitude.  Most devices will work OK with your configuration at room temperature, but you need to build in some margin due to component tolerance and variances with the crystal, TCAN4550-Q1, and load caps may result in some errors across different operating conditions.

We recommend a series "dampening" resistor to be placed between the OSC1 pin and the crystal which can be used to reduce the current flowing through the crystal and lower the power dissipation or "drive level" that results in a lower oscillation peak-to-peak amplitude effectively "dampening" the amplitude.  Typically a resistor value less than 100ohms is sufficient.  

If a series resistor is not included in the application, then increasing the capacitor values will be required to increase the load and to add enough capacitance across the full temperature range to compensate to the changing parasitic capacitance that can lead to a possible clock mode switch.  Because your schematic does not have a series resistor, I would recommend increasing the load capacitors by 2-3pF each and see if you can't increase the minimum voltage level of the oscillation on the OSC2 pin.

Please review the datasheet that shows this recommended resistor and also the TCAN455x Clock Optimization and Design Guidelines Application Report (Link) for more information.

Regards,

Jonathan