Part Number: DP83867IR
Hi team
I have a customer who is using the DP83867IRPAP 10/100/1000 Ethernet PHY with i.MX RT1189 MCU. The MCU supports both RGMII and MII interfaces on shared pins for traditional Ethernet at 10/100/1000 and EtherCAT at 10/100, respectively. He has selected the DP83867IRPAP for its support of both RGMII and MII in the same device; however, the GTX_CLK and TX_CLK are on separate pins, complicating the design. He is wondering if it is possible to short these two pins in the layout, selecting in software from where the clock should be sourced. Is the TX_CLK pin in tri-state while in RGMII mode?
Regards,
Shaury
