Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: ALP
Hi team
Customer is going to use our 953/954 in their camera module. But they need to configure the register based on below requirement.
The CSI_CLK output from the 954 is dual-clock on the hardware side. However, since the customer's previous camera configurations all used single-clock, please configure the CSI_CLK as single-clock. The host side provides an external sync signal to GPIO_0 (Pin 17, FSIN) of the 953, a reset signal to GPIO_1 (Pin 18, RST), and a write protection signal for FLASH to GPIO_2 (Pin 27, WP). The reset signal pulse width is 50 µs, and the external sync signal frequency is 30 Hz.
Can you please share the recommended register configuation file?
Br
Hanbing
