• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 34 subscribers
  • Views 112 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65MLVD080: SN65MLVD080: Can D (Driver Input) and R (Receiver Output) be connected to a single FPGA bidirectional I/O?

Rohith M
Prodigy 10 points

Part Number: SN65MLVD080

Hi TI Team,

I am using the SN65MLVD080 in a half-duplex M-LVDS application with an FPGA.

To reduce FPGA I/O count, I am evaluating whether the Driver Input (D) and Receiver Output (R) pins of each channel can be connected together and interfaced to a single FPGA bidirectional (tri-state) I/O.

I would like to understand whether directly connecting D and R together is a supported or recommended implementation.

image.png

My questions are:

1. Can D and R be directly shorted together and connected to a single FPGA bidirectional I/O?
2. If not, what prevents this approach? Is it due to output contention, internal device architecture, or another limitation?
3. Is there a TI-recommended circuit to achieve a single FPGA data I/O per channel using this transceiver?
4. If direct connection is not recommended, would adding external components (such as a resistor or logic gate) make this implementation acceptable?

Thank you.

  • +1
    TI__Genius 16996 points

    Hi Rohith, 

    I don't think shorting the D and R pins together will work. Let's say at time=0, everything is LOW (D, R, and the MLVDS bus). The R pin is a push-pull output (see image below), which means when it is driving LOW, the top FET is open and the bottom FET is closed, essentially shorting the line to GND. If you then try to drive the line HIGH from the FPGA pin, the R pin will stop this because it will sink all the current from the FPGA pin to GND, keeping to voltage on the line LOW. I unfortunately don't know of a way to achieve this bidirectional I/O functionality with a resistor of logic gate. You could try to use a 2:1 mux, but you would need a way to select the mux channel, which would require an extra pin from your FPGA, defeating the purpose of the bidirectional I/O. 

    Regards,

    Matt

  • 0 in reply to Matt Smith
    Prodigy 10 points

    Hi Matt,

    Thank you for the detailed explanation. That clarifies why directly connecting the D and R pins is not a viable approach with the SN65MLVD080.

    I appreciate your time and the clear explanation.

    Thanks again!