Part Number: DP83867IR
We are using the DP83867IRPAPT in our design. It is connected to an ASIC with an MAC running GMII. We have hit an issue where we can't get the MDIO pin to stop driving the line low when it is out of reset. I'll place details, tests, and results below, and also the schematic of how the PHY is connected. PHY is allowing us to run at 100 Mb, but we need MDIO negotiations up and running to reach higher speeds.
- When the host writes to the PHY over MDIO, the line only reaches half-rail because the PHY is pulling it down. We can see that the PHY still accepts writes, as we can toggle the LEDs on the RJ45 on and off via MDIO writes. We never see the PHY attempt to write back on the MDIO line to the host.
- The PHY is still operating at 100 Mb speeds, so we know it is not experiencing a system-wide issue.
- When the PHY is placed in reset, the MDIO line floats back to the pull-up rail voltage of 1.8V.
- We forgot to add strapping resistors to the strap pins, but we did strap pin 53 after the fact to ensure it doesn't enter an invalid state, since states 1 and 2 aren't valid. We confirmed it straps at 1.46V.
- RBias is at 1.0V as expected
