Part Number: DS90UB947-Q1
Hi Team,
Can you advise me on my questions bellows:
Q1.
When DS90UB947 is set Dual ODLI input mode and manually configured in Dual FPPD LINK III mode by setting register address 0x58 bit[1:0] = “11”b, should the pixel clock toggle once in every seven data bits as shown in the Figure 13, or toggle twice in every seven data bits?
The DS90UB948 data sheet insists as bellow, on page 41.
This makes me confused.
7.4.1.2 1-Lane FPD-Link III Input, Dual Link OpenLDI Output
The input RGB data is split into odd and even pixels starting with the ODD (first) pixel outputs D0 to D3 and then the EVEN (second) pixel outputs D4 to D7. The splitting of the data signals starts with DE (data enable) transitioning from logic LOW to HIGH indicating active data.
In this configuration the PCLK rate embedded within the 1-lane FPD-Link III frame can range from 50 MHz to 96 MHz, resulting in a link rate of 1.75 Gbps (35 bit × 50 MHz) to 3.36 Gbps (35 bit × 96 MHz). Each LVDS data lane operates at a speed of 7 bits per 2 LVDS clock cycles, resulting in a serial line rate of 175 Mbps to 336 Mbps. CLK1 and CLK2 operate at half the rate as PCLK with a duty cycle ratio of 57:43.
Q2.
When DS90UB947 is manually configured in Dula FPDLINKIII mode, should the DS948 be also manually configured in Dula FPDLINKIII mode?
Mita
