DS90UB936-Q1: FCT Failures - VCAN Camera_Frames_Counter -

Hi Applications Team,

ATE and Bench Verification of 4 returned units reported by Aptiv with this issue was completed under QEM-CCR-2605-00603 and QEM-CCR-2605-00850.

Bench Verification was performed using the device's default register settings and also using the customer's application register settings. 

ATE Verification was performed by Harry Nguyen. Bench Verification was performed by Skylar Kennett.

A non-conformance of device behavior was not observed. the 8D report is available under the Attachments of QEM-CCR-2605-00603.

The Quality team believes this may be an application-level issue. Please provide the appropriate support to Aptiv. Thank you.

I am still needing support on it, please let me know if I need to provide further details

Hello Oscar,

I am syncing with the internal team to provide additional support.

Quick summary so far:

1. Failure Mode: In the "suspect" units, when the ECU starts, the unit continuously reboots. LOCK is being lost repeatedly.
2. Passing Mode: In the Master units (working use case), the ECU starts, runs some config script, and everything is fine.
3. ABA swap was performed with the "suspect" units and the issues seem to follow the UB936 chip.
4. Main Power Supplies in the system were measured.
   1. A power supply called "POC_DIAG" is measuring much lower voltage than expected (about 0.552V than the expected 1.2V).
5. The UB936 power rails were probed and there were no abnormal voltages at the UB936 power pins.

Follow-Up Questions:

1. Where is "POC_DIAG" measured at? Is it a voltage rail on the deserializer or the serializer?
   1. Is this perhaps some type of "power good" signal outputted by a PMIC or power IC?
2. Just to double-check, when you probed the UB936 power rails, did you probe at the decoupling capacitors near the IC power pins? Or the side of the ferrite bead facing the IC power pins?
   1. 
3. What MODE are you operating at?
   1. Synchronous or Non-Synchronous?
4. What is the connected serializer chip?
   1. E.g. UB935?
5. In the slides that were shared over email, it seems that when the "IMAGER_RESET" signal is pulled LOW, LOCK on the UB936 is also pulled LOW.
   1. Is this expected?
   2. Does this unstable LOCK behavior only occur at power-up of the system when the "suspect" chips are populated? Or does the unstable LOCK behavior only occur when the "IMAGER_RESET" signal is sent?
   3. I'm trying to understand the full failure conditions in more detail, to see if there are any clues that can help narrow down the issue.
6. Were you able to get reg dumps of the system in the Passing Mode and the Failing Mode?
   1. This seemed like an action item over email, but it seems there were issues with getting I2C writes.
7. In the failure condition, are all of the power rails to the serializer fine?
   1. Are you able to measure the voltage rails directly on the serializer in the Failing Mode?

Would you also like to continue this debug over email? This is a public E2E forum, so anyone online can see these responses. I don't believe the information we are talking about for this debug is sensitive, but please let me know if I am wrong.

Best,

Justin Phan

Hello Justin, thank you for your feedback,

actually, yes, I would prefer to follow up via Email,

in regards your questions, I will share with my team in order to respond as soon as possible

Hello Oscar,

Yes, please let me know. You may also ask Maaha to add me to the email thread with the relevant parties, if there is an existing one with the latest debug status.

Best,

Justin Phan