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TRS3243E: TRS3243E output waveform slope change after long idle period

Part Number: TRS3243E

Hi team,
 
Background:
We are evaluating TRS3243E (3.3V supply, 0.1µF charge-pump capacitors) in a loopback configuration (TX-RX, RTS-CTS).
We observed that the RS-232 output falling edge sometimes shows a two-slope behavior, especially after the output stays in the HIGH (negative RS-232 level) state for a relatively long time. Communication works correctly without errors.
Questions:
  1. Is a multi-slope (non-linear) falling edge waveform considered normal behavior for TRS3243E drivers?
  2. Does the internal charge-pump regulation (V+/V− behavior during idle) affect transient output slew characteristics depending on idle duration?
  3. Are there any application notes or characterization data describing waveform dependence on idle time or charge-pump state?

Best Regards,
Ryu.

  • Is a multi-slope (non-linear) falling edge waveform considered normal behavior for TRS3243E drivers?

    I have seen it before in RS232 drivers. I think what happens here is that the PFET and the NFET might be in slight contention with each other for a short time before the PFET turns off entirely and the NFET takes over.

    Since the signal isn't truly non-monotonic (meaning we don't see a large spike in the opposite direction), it shouldn't cause any signal integrity problems.

    The FETs are also sized to handle short circuits so the short duration of the contention shouldn't damage the device. 

    Does the internal charge-pump regulation (V+/V− behavior during idle) affect transient output slew characteristics depending on idle duration?

    I don't think so. As long as the charge pump circuit is regulating the voltage correctly the slew rate characteristic shouldn't change too much when idle.

    Are there any application notes or characterization data describing waveform dependence on idle time or charge-pump state?

    I'm not aware of any documentation around this topic. 

    -Bobby