DS90UB947-Q1EVM: How t configre Dual OLDI mode

Nikolas-san,

Thank you for your answer.
However,. I still have question.

I configured DS90UB947 in Dual OLED mode.
So, the payload rate is double of the PCLOCK.
If the PCLK is toggling at 75MHz, payload rate is 150 M pixel/s.
It may be split into two FPDLINK III lanes.

Then, DS90UB948 merges the split payloads into one 150 M pixel/s stream.
Finally, the 150 M pixel/s stream is split into two OLDI streams which data
rate is 75 M Pixel/s each.
If my comprehension is correct the PCLK comes out from DS90UB948 should be 75 MHz
Instead of 37.5MHz.

If the auto rate detection in DS90UB947 simply measure the input clock frequency
Regardless of Single/Dula OLDI mode, the devices behave as I see.
Is my suspicion is correct?

Mita

Nikolas-san,

Thank you for your answer.

Your answer is well coincide my understanding, however, different from my observation.

When I applied 75 MHz clock to the DS90UB947 in Dual OLDI mode, 37.5 MHz clock
from DS90UB948 in Dual OLDI mode.

I wonder if you can check it in the LAB using EVMs?
Please allow me to be sticky on this topic for a while.

Mita

Hi Mita-san,

Can you draw a block diagram of your exact observations? Please denote what exact CLK frequency (in MHz) is being input/output at each individual port.

Best,

Nikolas

Nikolas-san,

Thank you for your feedback.
Bellow is the block diagram of my test set up.

I used LMK03328EVM as a clock source. A pulse pattern generator can be used as an alternative source.
The SAM cables are soldered to fly wires and connected to the LVDS clock inputs of the DS90UB947.
A LVDS clock output is monitored using an oscilloscope trough a probe.

Mita

Hi Mita-san,

What is the exact frequency being output by the LMK03328EVM? Can you provide some more specificity on how that EVM works?

Best,

Nikolas

Nikolas-san,

As I reported before, I set both DS90UB947 and DS90UB048 in Dual OLDI mode,
applied 75 MHz AC LVDS clock to DS90UB947 and monitored the output clock
from DS90UB948. It was half of the input clock(37.5MHz).

When I increased the input frequency to 150MHz, the output frequency was
increased to 75 MHz.

Lest of the settings were same as default settings.
When I tested the EVM, I used STP cable instead of Coax.

Because I have another trouble, when I used coax cables.
The EVMs DS90UB948 was properly locked to the input with STP cable..

Mita

Nikolas-san,

Here are detail my settnigs for the eval boards.

Mita

Hi Mita-san,

From what you are describing, what you are observing is expected but perhaps there is a lapse in my understanding of your test set-up. This is my interpretation of your set-up,

Based on my understanding of your previous response, "applied a 75MHz AC LVDS clock to DS90UB947" means that the total PCLK being driven to the device is 75MHz, not necessarily a per-port OLDI CLK of 75MHz. Please correct me if I am misunderstanding.

Best,

Nikolas

Nikolas-san,

Thank you for your feedback.
Your comprehension seemed to be bit different from my test set up.
I have attached correct version as bellow.
Can you please check it out.

Mita

Nikolas-san,

Thank you for your feedback.

Yes, I have a critical question.
Please provide me the answer to my question.

Question:
Can you configure DS90UB947 and DS90UB948 to transfer 1080p60 video signal
using DUAL OLDI input and Dual OLDI Output mode?

In DUAL OLDI input and Dual OLDI Output mode, Pixel clock rates on input and output
should be same, but DS90UN947/948 doesn’t realize.

Mita

Nikolas-san,

Thank you for your reply.

I am a bit confused.
Please bear with me a little longer as I try to resolve my questions.

Looking at Figure 13, the odd and even pixels are mapped to D0–D3 and D4–D7, respectively.
This means that if the system operates with a 75 MHz clock, 150 M Pixel/s of data are input into the UB947.
Do you agree?

Next, let's look at the UB948 output.
As mentioned at the beginning of this thread, when a 75 MHz clock is input to the UB947,
the UB948 outputs a clock at half that frequency—37.5 MHz.
Regarding the UB948 output, odd and even pixels are output simultaneously within a single clock cycle.
The resulting data rate is 37.5 M Pixel/s × 2 = 75 M Pixel/s.
Do you agree?

The output data rate is half of the input data rate.
Where does the remaining 75 M Pixel/s of data go?

Mita

Esther-san,

Thank you for your reply.
Here is my ultimate question.

The diagram below is from the DS90UB947 datasheet.

Question 1:

Is it possible to transmit the UB947's LVDS inputs D0–D3 to
the UB948's D0–D3 via DOUT0, and the UB947's LVDS inputs D4–D7 to
the UB948's D0–D3 via DOUT1?

Question 2:

In that scenario, is there a way to keep the frequency of the
UB947's LVDS clock input and the UB948's LVDS clock output the same?

Question 3:

If that is not possible, is using a single OLDI input the
only way to transmit a 1080p60 format image?

Mita

Esther,

I would appreciate it if you could answer my previous questions.

Mita

Hi Mita-san,

I will be covering this thread again while Esther is OoO.

I think we should take one step back here. A combination of a UB947 serializer --> UB948 deserializer is a very common configuration that is utilized to drive 1080p video, irrespective of the UB947 OLDI strap, FPD-Link strap modes, and UB948 strap modes.

With that in mind, can you provide more details on your system-level architecture? What is the OLDI format being output by your source? And what is the OLDI format expected to be input at your display?

Best,

Nikolas

Nikolas-san,

Thank you for your reply.

I Understood it.  Below is a conceptual block diagram.

The SoC generates a 1080p60 image.
The FPGA then converts this image into two OLDI streams.

Each OLDI stream consists of four LVDS lanes (serializing
7 bits each) and a 75 MHz clock.
Each OLDI stream simultaneously outputs adjacent odd and even pixels.

The Dual OLDI signals output from the FPGA are input into the UB947.
The UB948 expects to output the data received by the UB947 in its
original format.

In other words, if the UB947 and UB948 were bypassed, the Dual
OLDI signals output from the FPGA would be input directly into
the LCD panel and displayed.
So, the binput clock frequency and output clock frequency must be
same.

Mita

Hi Mita-san,

Thank you for sharing the block diagram - the context regarding the FPGA and LCD panel is much appreciated.

However, it looks like what you described in text does not match what is described on the block diagram. If each OLDI stream has its own CLK at the FPGA output, then this would be independent OLDI and not dual OLDI. Independent OLDI allows each OLDI port to operate on its own (with one CLK lane and four data lanes each, so two CLK lanes and eight data lanes total), whereas dual OLDI allows both OLDI ports to operate together (with one CLK lane and eight data lanes).

Independent OLDI is typically used to drive two separate images, whereas dual OLDI is often used to drive one image. Can you possibly clarify what exactly is being output from the FPGA?

Best,

Nikolas