Part Number: AM62L
Hi,
We have a few questions regarding our AM62L DDR4 design.
Since we could not find an AM62L DDR4 reference schematic or design example, we completed our schematic based on the available documentation and used direct DQ mapping (DQ0→DQ0, DQ1→DQ1, etc.).
Later, while reviewing AM62x DDR4 reference designs, we noticed that some DQ signals are swapped within the same byte lane to simplify DDR routing and BGA fan-out.
Our current schematic has already been reviewed and there is no issue with the existing connectivity. However, before starting the PCB layout, we would like to understand whether the same DQ bit swapping approach can also be applied to AM62L DDR4 designs if it helps routing.
Additionally, could you please provide the recommended trace impedance targets for AM62L DDR4 routing for both 4-layer and 6-layer PCB stack-ups?
Specifically, we would like to confirm:
- Single-ended impedance for DQ, DM, Address, Command and Control signals
- Differential impedance for CK_P/N and DQS_P/N signals
Thank you for your support.
Best regards,
Rümeysa Tuba Seven Iyiso
