Part Number: DP83869HM
Hi team,
I am currently working with the DP83869HM Ethernet PHY and trying to configure GPIO1 as a Wake-on-LAN (WoL) indication pin.
According to Section 7.3.1 of the DP83869HM datasheet:
"When a qualifying WoL frame is received, the DP83869HM WoL logic circuit is able to generate a user-defined event (either pulses or level change) through any of the GPIO pins or a status interrupt flag to inform a connected controller that a wake event has occurred."
This confirms that a GPIO pin can be used to indicate a WoL wake event. However, I could not find a clear description in the datasheet regarding the output polarity of GPIO1 when configured as a WoL indicator.
My questions are:
- When GPIO1 is configured as a WoL indication output, what does High level represent and what does Low level represent?
- Is the default behavior Active High (GPIO1 goes HIGH when a WoL frame is detected) or Active Low?
- Is there a polarity invert bit available to reverse the output polarity of the GPIO pin in this mode?
- Which specific registers need to be configured to set GPIO1 as a WoL indication pin (e.g., GPIO Mux register, WoL configuration register)?
Any clarification or register-level guidance would be greatly appreciated!
Thank you in advance.
