Part Number: DS90UB941AS-Q1
Hi experts,
I have a FPD3 serializer/deserializer system with an effectiv pixel clock of 148.5 MHz (2200x1125@60Hz).
In the ub941 data sheet there is this equation:
f_pclk = f_dsi * 12 / n_lanes
For a system with 4 lanes this results in f_dsi = 445.5 MHz and a line rate of 891 Mbps.
My question now is:
Must the DSI host's PHY run with exactly this rate?
Is it possible to use a higher line rate, e.g. 950 Mbps, when the host adapts sending of sync packets (VSS, VSE, HSS, HSE) to achieve the original timing?
What must be programmed into ub941? I've seen registers DSI_PCLK_DIV_M and DSI_PCLK_DIV_N - are they used to adjust this relationship?
Any help is very appreciated!
Best Regards,
Josef