DS90UB941AS-Q1: Relationship PCLK and DSI_CLK

Part Number: DS90UB941AS-Q1

Hi experts,

I have a FPD3 serializer/deserializer system with an effectiv pixel clock of 148.5 MHz (2200x1125@60Hz).
In the ub941 data sheet there is this equation:
f_pclk = f_dsi * 12 / n_lanes
For a system with 4 lanes this results in f_dsi = 445.5 MHz and a line rate of 891 Mbps.

My question now is:
Must the DSI host's PHY run with exactly this rate?
Is it possible to use a higher line rate, e.g. 950 Mbps, when the host adapts sending of sync packets (VSS, VSE, HSS, HSE) to achieve the original timing?
What must be programmed into ub941? I've seen registers DSI_PCLK_DIV_M and DSI_PCLK_DIV_N - are they used to adjust this relationship?

Any help is very appreciated!

Best Regards,

Josef

  • Hi Josef,

    I have a FPD3 serializer/deserializer system with an effectiv pixel clock of 148.5 MHz (2200x1125@60Hz).
    In the ub941 data sheet there is this equation:
    f_pclk = f_dsi * 12 / n_lanes
    For a system with 4 lanes this results in f_dsi = 445.5 MHz and a line rate of 891 Mbps.

    You are correct, this would be the correct DSI clock frequency and DSI rate.

    Must the DSI host's PHY run with exactly this rate?
    Is it possible to use a higher line rate, e.g. 950 Mbps, when the host adapts sending of sync packets (VSS, VSE, HSS, HSE) to achieve the original timing?

    It is typically recommended for the host to run at the corresponding DSI rate, this way the 941AS can run in DSI Reference Clock mode and use the provided DSI clock. Is there a reason you do not want to use this method?

    It is possible to run at a higher rate, but there are additional considerations that need to be taken with additional programming of the device. I would need to check with some colleagues on the specifics of what is needed.

    What must be programmed into ub941? I've seen registers DSI_PCLK_DIV_M and DSI_PCLK_DIV_N - are they used to adjust this relationship?

    Here is an example script for initializing the 941AS. This uses DSI0, and is for DSI Reference Clock mode:

    ## Pixel Clock = 148.5 MHz (eg. for standard 1080p)
    
    ## DSI clock = PCLK * 12/(# of DSI lanes) 
    
    ## DSI clock = 445.5 MHz
    
    ## DSI input port 0
    ## 4 lanes DSI
    
     
    import time
    
    serAddr = 0x18
    desAddr0 = 0x58
    
    #RESET 941
    board.WriteI2C(serAddr,0x01,0x02)
    
    #Disable DSI
    board.WriteI2C(serAddr,0x01,0x08)
    
    board.WriteI2C(serAddr,0x1E,0x01) # Select DSI0
    board.WriteI2C(serAddr,0x4F,0x8C) # Set single DSI0 mode - continuous clock mode
    
    board.WriteI2C(serAddr,0x40,0x04) # TSKIP_CNT DSI0
    board.WriteI2C(serAddr,0x41,0x05) # TSKIP_CNT DSI0
    board.WriteI2C(serAddr,0x42,0x30) # TSKIP_CNT DSI0, TSKIP_CNT (dec)= 24
    
    
    board.WriteI2C(serAddr,0x40,0x04) # Set HSYNC/VSYNC Polarity DSI0
    board.WriteI2C(serAddr,0x41,0x21) # Set HSYNC/VSYNC Polarity DSI0
    board.WriteI2C(serAddr,0x42,0x60) # Set HSYNC/VSYNC Polarity DSI0
    
    
    board.WriteI2C(serAddr,0x40,0x10) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(serAddr,0x41,0x86) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(serAddr,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(serAddr,0x41,0x94) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    board.WriteI2C(serAddr,0x42,0x0A) # Init DSI Clock Settings (From Section 10.2 of datasheet)
    
    #Enable DSI
    board.WriteI2C(serAddr,0x01,0x00)

    Best,

    Cameron

  • Hi Cameron,

    thanks for your reply.

    The reason for this is the need of flexibility. Our product is a controller box that provides the possibility of connecting a display via FPD Link. One customer has the above mentioned panel, but others may need different. In our box, video timing on the MIPI DSI interface is software programmable, but the line rate is fixed.

    So a guide on how to program this into the ds90ub941 would be very helpfull.

    Best regards,

    Josef

  • Hi Josef,

    I see. In that case, I believe what you will need to do is send the DSI data in 'burst mode' from your box and the use an external REFCLK signal on the REFCLK pins of the 941AS. This mode does not explicitly use HS/VS signals coming from the DSI interface since the DSI rate is too high for the PCLK of the signal being sent. Instead, this mode requires that the HS and VS widths be programmed into the serializer via the DSI_HSW_CFG and DSI_VSW_CFG indirect registers. Please see the 941AS bring up guide for more information and details:

    This document has good information on burst mode as well as the other clocking modes that should help you get your 941AS up and running. 

    Please let me know if you have any additional questions.

    Best,

    Cameron

  • Hi Cameron,

    thanks again for your answer.

    I'm still wondering if it is also possible to use DSI Reference clock mode also for burst mode?

    And it's still not clear to me how PCLK is regenerated from DSI clock. Is there a PLL inside the chip? And what are the above mentioned registers  DSI_PCLK_DIV_M and DSI_PCLK_DIV_N used for? Is there any further description for them available, as there is nothing neither in the data sheet nor the DSI bringup guide.

    If only burst mode with external refclk is possible: how to setup this?
    In the DSI bringup guide in chapter 2.2 is said:
    "Although it is possible to apply different clock rates between REFCLK and DSI clock in this mode, the implications for such a configuration are outside the scope of this document"
    Can you may give support for this?

    Best,
    Josef

  • Hi Josef,

    I need to discuss this with some colleagues, I will get back to you on Monday with an update.

    Best,

    Cameron