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DP83TC815EVM-MC: DP83TC815EVM-MC Master Link-Up time

David Wenninger
Prodigy 20 points

Part Number: DP83TC815EVM-MC

Hello,

 

i have a question regarding the link-up time of the DP83TC815 PHY as Master.

 

We are using two identical EVMs without modifications. The jumpers are set to autonomous mode on both boards. Furthermore, one of them is configured as slave and the other as master.

The PHYs are both powered via USB and a SPE link is established with a suitable UTP cable. The TX PHYs where not connected externally.

The goal was to verify the link-up times of both link partners after power up or hard reset.

 

For that we reset the PHY via the reset button and measured the link-up time with the corresponding registers (0x4EE, 0x4EF). As a second measurement we looked at both the reset pin and the link LED with an oscilloscope.

On the slave side that time amounted to roughly 40ms for a series of measurements. This is acceptable and matches expactations.

However, on the master side, the link-up took up to 10 seconds. And that durration was not consitent but rather volatile. At some occations the link-up seemed to be instant, then again as high as multiple seconds.

The question is, why the master side takes that long. And does it make sence that the salve side confirmes a link that much faster, than the master side?

 

We also tried switching the boards from master to slave and vice versa to rout out hardware failures. We got the same behavior no matter which board was what.

We also tried using a soft-reset via writing the corresponding register. We observed equally long durrations.

 

We are happy for any suggestions on what to try next or where we went wrong.

 

Thank you very much.

 

Kind regards,

David Wenninger

  • 0
    TI__Mastermind 28662 points

    Hi David,

    We have recommended initialization scripts for DP83TC815, which can be found here: https://www.ti.com/drr/opn/DP83TC815-Q1-DESIGN 

    Can you please load the initialization scripts (or confirm if you are already) and let me know if the behavior changes?

    Thanks,

    David

  • 0 in reply to David Creger
    Prodigy 20 points

    Hello,

    thank you for the reply.

    Running both EVMs in managed mode and loading the recommended initialization resolved the issue. The link-up time is now below 100ms, which matches expectations.

    However, a new question has come up:

    Many of the registers that are being changed in the recommended initializatioon for both master and slave are not described in the datasheet. We would like to understand what we are changing here. Could you please provide additional information on these registers?

    Thanks,

    David

  • 0 in reply to David Wenninger
    TI__Mastermind 28662 points

    Hi David,

    Glad to hear this resolved the issue. These registers adjust internal Digital Signal Processing blocks (gain, timing, etc.) to provide best link up times as you have noticed. These registers should be written exactly as shown in the order given without modifications. 

    Thanks,

    David