Part Number: SN65HVD1473
Hi team,
My customer is considering the SN65HVD1473.
Their system operation involves scenarios where some nodes are powered OFF while other nodes continue to communicate.
When a signal is applied to the bus lines (A/B pins) while a node's power is at 0V, what measures are in place to prevent the following issues:
Backfeeding to the VCC side through internal protection elements?
Reduction in input impedance during power-off states?
Bus noise during power-up and power-down sequences?
Best regards,
Kazuki Itoh