TUSB8041: TUSB8041IRGCR

Hi,

Unfortunately, the TUSB8041 does not have adjustable settings to increase the eye height.

I have some questions:

1) Can you share the schematic of the implementation

2) Can you share a layout of the implementation? There may be some fixes in design that can address this issues.

our schematic and test on port1 (JIO1)

Hi Simon,

I don't any major issues in the schematics shared. Are you able to share a layout?

below is our layout, JIO1 had add 30 com cable to I/O.
our layout trace and cable not over 3m.

Hi Simon,

simon lee said:

below is our layout, JIO1 had add 30 com cable to I/O.
our layout trace and cable not over 3m.

Hi Simon,

This 3m cable length is derived from loss spec. What is the total post-channel (hub to connector) loss of the system?

insertion loss:
TUSB8041 = ?
M/B trace= 1.15
cable = 3db

I/O board = 1db

Hi Simon,

Got it. Is CTLE enabled for the far end eye on the scope where this testing is being done? 

Can you share the full compliance report?

Please check our test report
USB1.pdfUSB0.pdf

Hi Simon,

Thanks for the reports. Based off of what I can see, I cannot determine if CTLE is performed on these waveforms. 

Here is a sample compliance report for 5Gbps TX compliance. The software used is Keysight. In this case we can see that STLE (continuous time linear equalization) is applied to the far end signals. This will boost the signal and provide more margin. This is standard procedure for the TX eye diagram test.

3m_pre_compliance.pdf

I cannot see if this setting was enabled in the reports shared, can you confirm that this is enabled for these tests?

We check with our SI team, our test not to enable the CTLE.
Could hlep let us know in which USB-IF specification the CTLE setting is defined and can be enabled?

We had check with Tektronix for our SI test, that had enable the CTRL for test resolute.

Tektronix scope default had enabled for USB 3.1 5Gbps.

our desing had meet USB loss budgets.

Please let us know how to open the eye.

Hi Simon,

Got it Thanks for confirming that CTLE is being applied.

Can you share the full layout files for the boards? The MB and the IO board? I would like to fully review the design. Please send the full layout files.

Additionally can you confirm what kind of cable is used between the JIO connector and the IO board?

It may be worthwhile to test with different SMA cables and breakout fixtures, as the fail is very marginal. We have seen failures like this be resolved by swapping cables.

If possible can you share a block diagram of the setup?

Hi Vishesh:

please check below for block diagram and cable(30cm) IL value.

we had change the different cable for same part number, the eye not had significant change.

Add DSN and board file.  PW: 123
X15SOH-AP-R101-20260309-USB.zip

Hi Simon,

Thanks for the files. As per our meeting, I need the following info:

1) Compliance test setup. Should look something like this.

Because the fail is very marginal, testing with different cables/ fixtures may help the results.

2) Daughter board/ IO board layout.

3) internal cable used.