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DP83822HF: Recovering RxCLK from 10M Ethernet

Avner Cohen
Intellectual 490 points

Part Number: DP83822HF

Hi,

In my application I need to recover the Ethernet clock and use a pll to produce Audio clock.

The rate of the line is 10M (and not 100 nor 1G)

The switch that I use have RMII/RGMII only

That means the DP83822HF PHY that I am thinking of using must work in RGMII mode (MII does not exist.  RMII does not provide RX_clk)

In the data sheet it is written on the RX_CLK pin the followings:

“RGMII Receive Clock:RGMII Receive Clock provides a 25MHz reference clock for 100Mbps speed and a 2.5MHz reference clock for 10Mbps speed, which is derived from the receive data stream.”

So I want to feed the 2.5M to the PLL circuitry in order to produce the 24.576 Mz

It is clear that when there is  loss of link, ie, Ethernet is not connected then the RCX_CLK will not produce clock, and I can compensate on this.(by switch over of input to the pll circuitry) However I cannot compensate on gaped clock of non continues clock.

What I want you to please confirm and validate is does the RX_clk will output the clock continuously when the link is up especially when there are no exchange of packets  or the rate of the traffic is very low and the PHYs Rx_CLK should rely on the sync pulses exchanged by the PHYs.

Thanks,

  Avner

  • 0
    TI__Mastermind 38835 points

    Hi Avner,

    While the DP83822 remains linked up, the 2.5MHz clock should be stable regardless of data transmission. This clock is derived from the receive data stream, but would not change if data stops or starts transmitting (so long as the link itself stays up)

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Intellectual 490 points

    Hi,

    I am sorry that I stress this to be sure: I have seen the quoted part in which the data sheet states that 2.5Mhz clock will be available and I understand that you wrote that the RCLK clock will be available even with no traffic passing to the PHY. However, since I use this clock to pll circuitry that MUST have recovered clock from the distant unit , I want to be sure that the stable RCLK clock is always recovered clock from the line at all time while the link is ON. I stress this since other PHY and even the 10M standard as I understand it, does not support this at 10M but do support it in 100M.

    Looking forward  for your confirmation,

    Thanks,

      Avner

  • 0 in reply to Avner Cohen
    TI__Mastermind 38835 points

    Hi Avner,

    Let me look into this. I'll aim to update by tomorrow or friday.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    TI__Mastermind 38835 points

    Hi Avner,

    The 2.5MHz clock is recovered from the line only while data is received from the link partner. While the line is idle the PHY will transition the 2.5MHz clock to reference the local clock. When the link is idle at 10M there will only be periodic link pulses, so I do not believe a clock can be recovered in this state.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Intellectual 490 points

    Hi Shane,

    OK. so what is the packet rate to get stable clock ? for example, If I make sure to have packets sent at minimum every 4mS (which is approximately the software cycle) does the PLL mechanism inside the chip will be able to give a certain recovered clock ? 
    Regards,

      Avner

  • 0 in reply to Avner Cohen
    TI__Mastermind 38835 points

    Hi Avner,

    10Mbps ethernet will have an inter-packet gap between consecutive packets. During this phase, the line will be idle and a clock will not be recovered from the link partner. Regardless of how many packets are sent, there will be an inter packet gap between them where the clock will need to switch to the local reference.

    Are you able to use 100Mbps data? While 10base-Te stops signaling, 100base-TX sends an idle pattern when the line is not active. I believe the PHY will recover a 25MHz clock from this idle pattern, and can look into this if 100Mbps is a possibility for your application.

    Best,

    Shane

  • 0 in reply to Shane Hauser
    Intellectual 490 points

    Hi Shane,
    the cables we use are not set for 100M therefore we have to use 10M ethernet. 
    1) Is there other PHY by Ti that can guarantee, recovered clock at  10M (and that can accept RGMII mode? (not RMII nor MII)
    2) Do you have other TI IC solution if I want to pass clock over the ethernet (Sync-E) with 10M?

    Thanks,

     Avner 

  • +1 in reply to Avner Cohen
    TI__Mastermind 38835 points

    Hi Avner,

    1. No, we do not have a PHY that recovers a clock from the link partner in 10M during idle periods. 

    2. Unfortunately due to the nature of 10Base-T signaling, we do not have a solution that can recover a clock from the idle line. 

    Best,

    Shane