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DS90UB941AS-Q1: Power-up Sequence Issue of DS90UB941

fei huang
Prodigy 60 points

Part Number: DS90UB941AS-Q1

Hello TI Support,
Regarding the DS90UB941:
 
Our power supplies are 1.8 V and 1.1 V. We plan to power up the 1.1 V rail first, followed by the 1.8 V rail, with a 1 ms delay between the two power sequences.
 
Could you please confirm if this power-up sequence is acceptable?
 
Additionally, is it permissible to delay the assertion of the PDB pin to align with this power sequencing?
Thank you.
  • 0
    TI__Genius 11656 points

    Hi Fei,

    The sequence you described violates the 941AS power sequencing specified in the datasheet, so it would not be acceptable. 

    In total, there should be three supplies going into the 941:

    • A 1.1V supply for VDD11
    • A 1.8V supply for VDD18
    • A 1.8V OR 3.3V supply for VDDIO

    With these three supplies, the power up sequence should follow the following diagram:

    The values for the time variables in the above diagram can be found in Table 10-1 of the datasheet. Additionally, PDB should only be asserted after all three supplies are high, but it can be at any point after all three are high.

    BR,

    Cameron