SN65LVDS049: Technical Clarification on LVDS Interface Implementation Using SN65LVDS049

Part Number: SN65LVDS049

Hi Team,

I am working on the LVDS communication interface for the COMe-mEL10 carrier board and would like to confirm the proposed implementation.

System Overview

• External interface: Micro D-Sub connector

• LVDS Signals:

  • 1 × LVDS RX differential pair (External FPGA → COM module)

  • 1 × LVDS TX differential pair (COM module → External FPGA)

• COM module GPIO voltage: 3.3 V CMOS

• Target data rate: Approximately 100 Mbps

Proposed Implementation

I am planning to use the SN65LVDS049 transceiver as follows:

• R1 (Receiver 1): LVDS RX differential pair → 3.3 V CMOS output → COM GPIO Input

• D1 (Driver 1): COM GPIO Output → LVDS Driver → LVDS TX differential pair

The remaining channels (R2 and D2) will remain unused.

Clarifications Required

1. Is using only R1 and D1 of the SN65LVDS049 appropriate for this interface?

2. Is the SN65LVDS049 suitable for a 100 Mbps LVDS communication link in this application?

3. Can the Intel COM module 3.3 V GPIOs reliably receive and transmit 100 Mbps data through the SN65LVDS049, or are the GPIO timing limitations likely to be a bottleneck?

4. If GPIOs are not suitable for this data rate, what interface is recommended between the COM module and the LVDS transceiver (e.g., FPGA, PCIe, SPI, UART, or another high-speed interface)?

Please let me know if the proposed architecture is acceptable or if an alternative implementation is recommended.

Thank you.