Part Number: TUSB1210
FPGA : XAZU2EG ; It appears there is a bus contention. What is the root cause? Are there any risks?

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Hi Rita:
What is the pulse width for staircase?
Can you capture with DIR signal together? It could be turnaround cycle when DIR goes low.
Best
Brian
Hi Rita:
The location with staircase is a turnaround cycle. In turnaround cycle, either link nor PHY can drive the bus.
Data during turnaround cycle is undefined and should be ignored.
Regards
Brian