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TFP410: UXGA

ttd
Mastermind 9355 points

Part Number: TFP410

Dear Technical Support Team,

In my system, I’m using the following configuration:
FPGA → TFP410 → DVI-OUT

When outputting UXGA video, the eye pattern of the DVI output waveform is not very good, so I suspect jitter in the IDCK signal (generated at 162 MHz by the FPGA’s internal PLL) between the FPGA and the TFP410.

Question 1:
I am currently using IDCLK = 162 MHz in a single-ended configuration. Would a differential signal, such as LVDS, offer better resistance to noise and jitter?

Question 2:
Are there any precautions to take when using the TFP410 with UXGA?

Best Regards,

ttd

  • 0
    TI__Guru**** 190841 points

    TTD

    Yes, LVDS differential signal will be better than the single ended signal as it can reject common mode noise and create less EMI interference. 

    The TFP410 supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK− input (pin 56) should be tied to GND. Are they doing this in their design?

    In the differential clock input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK– signals as the timing reference for latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. Please note the differential clock input mode is only available in the low signal swing mode.

    The TFP410 does not care about the UXGA format. The TFP410 will work as long as the IDCK frequency is between 25 and 165MHz.

    Thanks

    David