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TUSB1310. PHY clk

sandesh shetty
Prodigy 10 points
Other Parts Discussed in Thread: TUSB1310, TUSB1310A

Hi,

 I have a board with a TUSB1310 USB 3.0 Transreciver. The board has a Xilinx Spartan6 board in which i have downloaded our Usb 3.0 Core. I have connected all the pins according the board specification.  However I have deduced from that the PCLK from the Phy is not received by our USB 3.0 Core and hence nothing is working as of now.

Is there any special requirement for the TI phy from the USB3.0 Pipe interface other than the standard PIPE interface signal.

Have tried to debug the cause and have come to the coclusion that Phy clk is not received. After going through the user manual I have found 2 signals which are out of my understanding.

1. RESETN

2. OUT ENABLE.

Kindly describe how these signals will affect the O/P of PHY Clk...

Is it necesary on the part of the USB 3.0 Link layer to drive this signals to actually get a valid PHY clKT

Thank You

  • 0
    TI__Guru* 76130 points

    Hello,

    The OUT_ENABLE needs to be set to "0" until all powers are stable in order to avoid a bus contention due to current draws.

    The RESETN latches strapping pin internally, starts effuse autoloading and sets all internal states to initial states. The Link Layer needs to hold the PHY in reset by the RESETN until all powers and the reference clock to the TUSB1310A are stable. All pins used for strapping options must be set before RESETN de-assertion.

    When PHY_MODE needs to be changed into other PHY modes, the RESETN needs to be asserted.

  • 0 in reply to Elias Villegas M.
    Prodigy 170 points

    Yes.We meet the same questions.These is nothing on the pclk pin.

    We have two board ,one solder TUSB1310 and the other solder TUSB1310A.The problem is that the board with TUSB1310A  can work correctly meanwhile the TUSB1310 doesn't generate the PCLK.

    We connect the OUT_ENABLE to GND through 10K pull down,and connect to FPGA pin at the same time.

    We connect the RESETN to FPGA pin.

    We generate the sequence of the reset through the FPGA.The FPGA holds OUT_ENABLE  '0' for a while and de-assert it before the RESETN goes to high.

    And how much time needed for the RESETN which keeps low??

    The strapping pins which needed to be set to '1' are pull up to 1.8v through 1K resistor.

  • 0 in reply to joey jiang
    Prodigy 100 points

    Hi,

    Have you tested with connect OUT_ENABLE to Logic high after power sequence stability?  Because as per datasheet we have to apply OUT_ENABLE high to generate PCLK.

    On more thing you have to take care is strapping for crystal frequency input selection. You must have to apply strapping value during RESET_N to generate proper PCLK frequency.

    Best Regards,

    Trupesh Vasoya