• State TI Thinks Resolved
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 35 subscribers
  • Views 91 views
  • Users 0 members are here
Support feedback
Options
Options
Related

TCA6424A: Timing requirements for RESET release during TCA6424A power-up

Kazuki Kumagae
Prodigy 10 points

Part Number: TCA6424A

Are there any timing requirements regarding the control and release of the RESET signal during the power-up sequence of the TCA6424A?

 For instance, if the RESET signal is controlled via software, are there any requirements or constraints concerning the power supply (VCCI, VCCP) ramp-up timing and voltage levels relative to the timing of transitioning the RESET signal from Low to High?

 If there are no such requirements, is it acceptable to transition the RESET signal from Low to High at an arbitrary time, regardless of the power supply ramp-up timing or voltage? If so, please explain the reason.

  • 0
    TI__Guru 61061 points

    We are still looking into this and will follow up soon.

  • 0
    TI__Guru 64838 points

    Hi Kazuki,

    I don't fully understand your use case, but we do offer some timing parameters and supply pin characteristics to help you time the /RESET pin. 

    The TCA6424A power-on reset circuit has a max of 1.4V according to the datasheet: 

    You would need to wait until VCCP is fully powered up to 1.4V before you could even initiate a /RESET command. 

    We also show some timing parameters for /RESET

    Regards,

    Tyler