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SN65DSI83-Q1: Driver support for DSI to LVDS bridge

Kiruthikram P
Prodigy 10 points

Part Number: SN65DSI83-Q1
Other Parts Discussed in Thread: SN65DSI83

Hi Team,

I'm working with the TI SN65DSI83 DSI-to-LVDS bridge on Linux platform (kernel 5.10.168) arm64. I couldn't find a suitable driver for this kernel version.

Could you please confirm whether the SN65DSI83 is supported on Linux 5.10.168 and, if so, provide the driver source file (ti-sn65dsi83.c) compatible with this kernel version. Please advise if you can make this driver available to us

  • 0
    TI__Mastermind 31480 points

    Hi Kiruthikram,

    Any drivers and programming tools are shared "as is" in this previous thread: [FAQ] SN65DSI8x Programming Tools

    I am not familiar about which linux versions can support the kernel versions.

    This device could also be programmed by entering the display timings, DSI config and LVDS config into the DSI Tuner GUI to generate the list of register settings. Then you can apply those register settings as part of the initialization sequence that is shown in the datasheet.

    DSI Tuner Guide: https://www.ti.com/lit/an/slla332b/slla332b.pdf

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 70 points

    Hi Haque,

    Thanks for the answer.

    After generating the register settings, if we write the register values directly through I²C, will that be sufficient to bring up the device? Once the device is initialized, can we use the LVDS display as a normal DSI display from the SoC side, with the DSI-to-LVDS bridge between them?



  • 0 in reply to Adithyan M
    TI__Mastermind 31480 points

    Hi Adithyan,

    Yes, the register settings written via settings are sufficient to bring up the bridge device. Please make sure you also follow the initialization sequence from the datasheet which has specific requirements for when DSI clock and data lanes, CSR register settings, delays, resets, etc.

    Test pattern: As a first step we would recommend using the internal test pattern so that the device generates video and outputs to LVDS. This will still require clock source (REFCLK or DSI clock input). This will confirm whether the downstream LVDS video to panel are correct timings and the interface is working.

    Video Input: After the test pattern is working, you can use  video input from DSI source (SoC side) and test end-to-end video. Please make sure you follow the initialization sequence. And if there are any issues, check the 0xE5 error flags and collect full register dumps.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 70 points

    . Please make sure you also follow the initialization sequence from the datasheet which has specific requirements for when DSI clock and data lanes, CSR register settings, delays, resets, etc.
    >>>>> So, are you saying that we need a basic driver to handle the required initialization sequence, and that simply writing the register settings alone is not sufficient for getting video ?

  • 0 in reply to Adithyan M
    TI__Mastermind 31480 points

    Hi Adithyan,

    The sequence can either be implemented within the driver, or you could set the sequence in relation to how the SoC is enabling DSI output.

    The initialization sequence requirements are shared in the datasheet in the "8.3.5 Initialization Sequence", and it mentions when the register settings have to be done in conjunction with the DSI input and enabling output. So the register settings have to be done following this sequence.



    Best regards,
    Ikram