TCAN4550: CAN interface stops receiving frames after some time

Himanshu Gupta

Part Number: TCAN4550

Hello,

We have used two TCAN device ( TCAN4550) on same SPI bus ( with different chip select),

During CAN-FD testing between the CAN interfaces, the receiving CAN interface stops receiving frames after some time. When this occurs, the interrupt counters stop incrementing, and CAN communication on the affected interface becomes non-functional.

Setup:

We have two TCAN4550 devices connected to a processor and are testing CAN-FD throughput and performance. We would like guidance on expected throughput limits and recommended validation methods.

Our setup consists of:

Host SoC: Linux based x86 processor.
Two TCAN4550 devices connected to the same SPI controller.
The two CAN interfaces are connected through external CAN gateways.
SPI clock configured at 12 MHz.
CAN-FD configuration:
- Arbitration bitrate: 1 Mbps.
- Data bitrate: 8 Mbps.
Linux Kernel: 15.
Driver: tcan4x5x / m_can.

Device Tree Configuration:

/* TCAN Devices */

can0: tcan4x5x@4 {

compatible = "ti,tcan4x5x";

reg = <4>;

spi-max-frequency = <12000000>;

clocks = <&tcan_clk>, <&tcan_clk>;

clock-names = "hclk", "cclk";

bosch,mram-cfg = <0x0 0 0 64 0 0 1 4>;

interrupt-parent = <&gpio2>;

interrupts = <10 8>;

reset-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;

status = "okay";

};

can1: tcan4x5x@0 {

compatible = "ti,tcan4x5x";

reg = <0>;

spi-max-frequency = <12000000>;

clocks = <&tcan_clk>, <&tcan_clk>;

clock-names = "hclk", "cclk";

bosch,mram-cfg = <0x0 0 0 64 0 0 1 4>;

interrupt-parent = <&gpio0>;

interrupts = <15 8>;

reset-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;

status = "okay";

};

CAN Interface configuration:

ip link set can0 up type can bitrate 1000000 dbitrate 8000000 fd on one-shot on restart-ms 100 berr-reporting on

ip link set can1 up type can bitrate 1000000 dbitrate 8000000 fd on one-shot on restart-ms 100 berr-reporting on

Current Test Method

Continuous CAN-FD traffic through CAN (can0->can1) while monitoring CAN socket statistics, Error and interface counters.

Test case 1: Traffic Flow: canFdTester à can0 -> TCAN4550-> CAN GATEWAY-> EXTERNAL LOOP -> CAN GATEWAY -> TCAN4550 -> can1 -> canFdTester

Test case 2: Traffic Flow: canFdTester à can1 -> TCAN4550-> CAN GATEWAY-> EXTERNAL LOOP -> CAN GATEWAY -> TCAN4550 -> can0 -> canFdTester

Traffic initially works correctly. After some time, TX continues normally but RX packet counters, RX byte counters and RX interrupts stop increasing on the receiving interface.

Interfaces remain ERROR-ACTIVE with TEC=0, REC=0, no bus errors and no bus-off events.

Logs:

root:~# ./canFdTester -t can0 -r can1 -s 500 -l 64 -b -a 1000000 -b 8000

000

CAN FD Tester TX=can0 RX=can1 FPS=500 Payload=64(64) BRS=ON Arb=1000000 bps Data=1000000 bps

Fr/s Payload/s TotalBits/s Speed(kbps) BusLoad% Err/s TEC REC BusOff State

------------ ---------------- ---------------- ------------ -------------- -------- ---------- ---------- ---------- --------------------

457/368 29248/23552 260033/209392 260/209 26.00/20.94 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

453/276 28992/17664 257757/157044 257/157 25.78/15.70 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

449/279 28736/17856 255481/158751 255/158 25.55/15.88 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

457/298 29248/19072 260033/169562 260/169 26.00/16.96 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

80/255 5120/16320 45520/145095 45/145 4.55/14.51 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

271/239 17344/15296 154199/135991 154/135 15.42/13.60 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

406/250 25984/16000 231014/142250 231/142 23.10/14.22 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

0/291 0/18624 0/165579 0/165 0.00/16.56 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

454/290 29056/18560 258326/165010 258/165 25.83/16.50 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

328/249 20992/15936 186632/141681 186/141 18.66/14.17 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

69/287 4416/18368 39261/163303 39/163 3.93/16.33 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

449/250 28736/16000 255481/142250 255/142 25.55/14.22 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

270/287 17280/18368 153630/163303 153/163 15.36/16.33 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

84/251 5376/16064 47796/142819 47/142 4.78/14.28 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

451/258 28864/16512 256619/146802 256/146 25.66/14.68 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

203/295 12992/18880 115507/167855 115/167 11.55/16.79 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

249/297 15936/19008 141681/168993 141/168 14.17/16.90 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

449/368 28736/23552 255481/209392 255/209 25.55/20.94 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

393/284 25152/18176 223617/161596 223/161 22.36/16.16 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

0/265 0/16960 0/150785 0/150 0.00/15.08 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

After some time

Fr/s Payload/s TotalBits/s Speed(kbps) BusLoad% Err/s TEC REC BusOff State

------------ ---------------- ---------------- ------------ -------------- -------- ---------- ---------- ---------- --------------------

432/0 27648/0 245808/0 245/0 24.58/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

435/0 27840/0 247515/0 247/0 24.75/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

439/0 28096/0 249791/0 249/0 24.98/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

114/0 7296/0 64866/0 64/0 6.49/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

434/0 27776/0 246946/0 246/0 24.69/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

428/0 27392/0 243532/0 243/0 24.35/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

434/0 27776/0 246946/0 246/0 24.69/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

431/0 27584/0 245239/0 245/0 24.52/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

435/0 27840/0 247515/0 247/0 24.75/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

436/0 27904/0 248084/0 248/0 24.81/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

435/0 27840/0 247515/0 247/0 24.75/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

439/0 28096/0 249791/0 249/0 24.98/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

433/0 27712/0 246377/0 246/0 24.64/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

438/0 28032/0 249222/0 249/0 24.92/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

434/0 27776/0 246946/0 246/0 24.69/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

437/0 27968/0 248653/0 248/0 24.87/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

299/0 19136/0 170131/0 170/0 17.01/0.00 0 0/0 0/0 NO/NO ERR-ACT/ERR-ACT

root:~# cat /proc/interrupts | grep -E "355|356|can0|can1"

355: 2099926 0 gpio_irq 10 can0

356: 1553986 0 gpio_irq 15 can1

root:~# cat /proc/interrupts | grep -E "355|356|can0|can1"

355: 2102237 0 gpio_irq 10 can0

356: 1553986 0 gpio_irq 15 can1 ß---- Interrupt counters freeze at receiving interface

root:~# ip -s -d link show can0

28: can0: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000

link/can promiscuity 0 minmtu 0 maxmtu 0

can <ONE-SHOT,BERR-REPORTING,FD> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 100

bitrate 1000000 sample-point 0.750

tq 25 prop-seg 14 phase-seg1 15 phase-seg2 10 sjw 1 brp 1

m_can: tseg1 2..256 tseg2 2..128 sjw 1..128 brp 1..512 brp_inc 1

dbitrate 8000000 dsample-point 0.600

dtq 25 dprop-seg 1 dphase-seg1 1 dphase-seg2 2 dsjw 1 dbrp 1

m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp_inc 1

clock 40000000

re-started bus-errors arbit-lost error-warn error-pass bus-off

0 0 0 0 0 0 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535 parentbus spi parentdev spi2.4

RX: bytes packets errors dropped missed mcast

124534144 1945846 0 0 0 0

TX: bytes packets errors dropped carrier collsns

124534144 1945856 0 0 0 0

root:~# ip -s -d link show can1

29: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000

link/can promiscuity 0 minmtu 0 maxmtu 0

can <ONE-SHOT,BERR-REPORTING,FD> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 100

bitrate 1000000 sample-point 0.750

tq 25 prop-seg 14 phase-seg1 15 phase-seg2 10 sjw 1 brp 1

m_can: tseg1 2..256 tseg2 2..128 sjw 1..128 brp 1..512 brp_inc 1

dbitrate 8000000 dsample-point 0.600

dtq 25 dprop-seg 1 dphase-seg1 1 dphase-seg2 2 dsjw 1 dbrp 1

m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp_inc 1

clock 40000000

re-started bus-errors arbit-lost error-warn error-pass bus-off

0 0 0 0 0 0 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535 parentbus spi parentdev spi2.0

RX: bytes packets errors dropped missed mcast

199239456 3113134 0 0 0 0

TX: bytes packets errors dropped carrier collsns

0 0 0 0 0 0

:~# ip -s -d link show can1

29: can1: <NOARP,UP,LOWER_UP,ECHO> mtu 72 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000

link/can promiscuity 0 minmtu 0 maxmtu 0

can <ONE-SHOT,BERR-REPORTING,FD> state ERROR-ACTIVE (berr-counter tx 0 rx 0) restart-ms 100

bitrate 1000000 sample-point 0.750

tq 25 prop-seg 14 phase-seg1 15 phase-seg2 10 sjw 1 brp 1

m_can: tseg1 2..256 tseg2 2..128 sjw 1..128 brp 1..512 brp_inc 1

dbitrate 8000000 dsample-point 0.600

dtq 25 dprop-seg 1 dphase-seg1 1 dphase-seg2 2 dsjw 1 dbrp 1

m_can: dtseg1 1..32 dtseg2 1..16 dsjw 1..16 dbrp 1..32 dbrp_inc 1

clock 40000000

re-started bus-errors arbit-lost error-warn error-pass bus-off

0 0 0 0 0 0 numtxqueues 1 numrxqueues 1 gso_max_size 65536 gso_max_segs 65535 parentbus spi parentdev spi2.0

RX: bytes packets errors dropped missed mcast

199239456 3113134 0 0 0 0 ß----- Rx counter not increasing at receiving interface

TX: bytes packets errors dropped carrier collsns

0 0 0 0 0 0

Observations:

We are testing CAN-FD traffic between the two TCAN4550 interfaces (can0 and can1) connected to the same MxL25641 SPI controller.

During testing, CAN-FD traffic initially flows correctly, and both interfaces show increasing RX/TX counters. However, after running for some time, we observe the following behaviour:

Transmission continues normally on the transmitting interface.
RX packets stop increasing on the receiving interface.
RX byte counters reported by ip -details -statistics link show stop increasing.
Interrupt count associated with the receiving TCAN4550 also stops increasing.
TX interrupt count and TX packet counters continue to increase normally.
CAN interfaces remain in ERROR-ACTIVE state.
No bus errors, bus-off events, or error counters are reported.
The transmitting interface continues to show increasing TX statistics, while the receiving interface appears to stop processing incoming frames.
During long-duration testing, the board occasionally becomes unresponsive and eventually reboots due to a watchdog timeout. Reset reason reported is ATOM WDT RESET.

Please help to point out the root cause for this.

22 days ago

0 Jonathan Nerger 22 days ago

TI__Mastermind 37941 points

Hello Himanshu,

Can you dump the device registers to a log so that I can review the device configuration and the value of the various Status and Interrupt registers?

Because your log files don't show any RX/TX Errors, or a Bus Off condition, I will need to see more detailed information about the device at the moment it stops receiving data. One possible reason a device would stop receiving data would be due to a Full RX FIFO or dedicated RX buffers preventing the device from storing any new messages.

Regards,

Jonathan

0 Himanshu Gupta 21 days ago in reply to Jonathan Nerger

Prodigy 30 points

Fullscreen SPI_REG_DUMP.txt Download

//can1
[diag] $ cat /sys/kernel/debug/regmap/spi2.0/registers                        
0000: 4e414354
0004: 30353534
0008: 00110201
000c: 08240008
0010: 3f3f0000
0014: 1f1f0113
0018: 00000000
001c: 00000000
0020: 000100ba
0024: 0000105c
0028: 0207f31b
002c: 00000000
0800: c80004a8
0804: 00000002
0808: 00000000
080c: 00000000
0810: 00000000
0814: 00000000
0818: 00000000
081c: 00000000
0820: 00000000
0824: 2001000d
0828: 00000000
082c: 00000000
0830: 8096a8ff
0834: 00000000
0838: 00000000
083c: 00000000
1000: 32150320
1004: 87654321
1008: 00000000
100c: 00800110
1010: 00000080
1014: 00000000
1018: 00000300
101c: 00001c09
1020: 000f0001
1024: 0000ca26
1028: ffff0000
102c: 0000ffff
1030: 00000000
1034: 00000000
1038: 00000000
103c: 00000000
1040: 00000000
1044: 0000300f
1048: 00000300
104c: 00000000
1050: 2001000d
1054: 3fffffff
1058: 00000000
105c: 00000000
1060: 00000000
1064: 00000000
1068: 00000000
106c: 00000000
1070: 00000000
1074: 00000000
1078: 00000000
107c: 00000000
1080: 00000000
1084: 00000000
1088: 00000000
108c: 00000000
1090: 1fffffff
1094: 00000000
1098: 00000000
109c: 00000000
10a0: 00400000
10a4: 03050540
10a8: 00000004
10ac: 00000000
10b0: 00001200
10b4: 00000000
10b8: 00000000
10bc: 00000777
10c0: 04001220
10c4: 00000004
10c8: 00000007
10cc: 00000000
10d0: 00000000
10d4: 00000000
10d8: 00000000
10dc: 00000000
10e0: 00000000
10e4: 00000000
10e8: 00000000
10ec: 00000000
10f0: 00041200
10f4: 00000000
10f8: 00000000
10fc: 00000000
8000: 1b0d4d86
8004: ff3f45d2
8008: e1aa57df
800c: 0792c4c6
8010: e6d336a5
8014: e3be0481
8018: 90edacbc
801c: 26f27963
8020: dd4429b5
8024: 1d51af48
8028: bda3764a
802c: aa5d72a8
8030: 4f5ad960
8034: b4a793b0
8038: 7db1b0f9
803c: 9e4d0035
8040: 75a6b852
8044: 2ecbbedd
8048: 1098c84c
804c: ff3f4674
8050: 2a671ef9
8054: 093e0f54
8058: 7dbf3a42
805c: 1f5815e2
8060: 85fcb903
8064: c956bf2c
8068: ec21d424
806c: 4ef0e9b2
8070: 73a63c5d
8074: eb0b2ebc
8078: 14a06086
807c: 01752143
8080: 1ac27b14
8084: fc992c5e
8088: 80b833f1
808c: 6aa899de
8090: 12298914
8094: ff3f4716
8098: 77543718
809c: 553774b7
80a0: e0230792
80a4: 5e3c3b62
80a8: 1ee91d39
80ac: a5d56594
80b0: 085bccfd
80b4: 9f762e1b
80b8: 05b5eec8
80bc: a1ac06c9
80c0: d2a6b4c4
80c4: fa4056f5
80c8: 154ccfb8
80cc: 2aad397f
80d0: 428d6c5b
80d4: 2c619bcf
80d8: 01d280e8
80dc: ff3f47b7
80e0: cd548d57
80e4: fac6b306
80e8: 0cb74490
80ec: 7f9bcd58
80f0: e583b272
80f4: 01b62b65
80f8: 7d3b845c
80fc: 2904c077
8100: 28f651cf
8104: a1300b81
8108: f9c918af
810c: 8e1dfaac
8110: 9f35d554
8114: 4a35aad8
8118: 1f1d9fdc
811c: aa818d6b
8120: 17e10bf0
8124: ff3f485a
8128: db5ed2eb
812c: ca6583e3
8130: 03b5760a
8134: d59c8ab9
8138: 6e4bff69
813c: e1cf2d19
8140: 6d33e046
8144: d0157d6f
8148: dec46328
814c: 42964284
8150: 44f076a3
8154: 48d09dd6
8158: c2bbb054
815c: d6862662
8160: 707b2374
8164: 57889979
8168: 82127331
816c: 77b3561c
8170: 19984ccc
8174: ff3f448e
8178: db2262cd
817c: 12f133ed
8180: 8f65a6d3
8184: 33c2f73b
8188: 14e6852d
818c: fd1645df
8190: 78d2f317
8194: 801f31f8
8198: 43e3f92c
819c: ba9c6aba
81a0: 936a4b53
81a4: 5217d83e
81a8: 321264a6
81ac: 35d6ad09
81b0: f19dbf67
81b4: aed06732
81b8: 1a558d2a
81bc: ff3f4530
81c0: 49310986
81c4: 6c754d1d
81c8: b2920d20
81cc: ce035763
81d0: 618e27bb
81d4: 7e6466cf
81d8: 559de1e8
81dc: eea21334
81e0: 94725635
81e4: 75c30e67
81e8: b6ba5599
81ec: 3622f047
81f0: 8396e15a
81f4: fcebc9b7
81f8: 83093705
81fc: 954ccafc
8200: 3896eb7d
8204: 99587efe
8208: b1b3eb74
820c: 2da09c13
8210: eadc7b3f
8214: f33c215b
8218: f09b0200
821c: 3756e7a6
8220: 05098284
8224: ff3f341a
8228: e815bab9
822c: 773329f0
8230: 926341c7
8234: 66eb8b66
8238: d4696088
823c: b4513a8d
8240: 3dd9fa4b
8244: 2df3070e
8248: 03f82c40
824c: 2accad96
8250: 2b1e45a3
8254: b83034fd
8258: 92f64298
825c: d22e74a0
8260: d0841095
8264: 772c4cee
8268: 0c74863a
826c: ff3f34bd
8270: 8cc7665f
8274: 0163c7e7
8278: cf8210fe
827c: 5b0d8a69
8280: b4fa316b
8284: 785d3812
8288: dd2dd325
828c: 7a8d06f6
8290: 67de184c
8294: 935d4120
8298: e91fe3d0
829c: a3cd73f4
82a0: 41c11975
82a4: 77485266
82a8: 22917fbc
82ac: dc3c40a7
82b0: 0c334618
82b4: ff3f355e
82b8: 8cd837ad
82bc: 5412b86a
82c0: 1efd5bd1
82c4: a495d20b
82c8: 523cb477
82cc: 6b933fb0
82d0: 15b552e1
82d4: b1be82ac
82d8: 74d193d2
82dc: f48df661
82e0: bcddd625
82e4: 6061c655
82e8: 2efd0dc8
82ec: 355edd74
82f0: d488113c
82f4: 332dac2c
82f8: 08fb047c
82fc: ff3f3601
8300: 91da2998
8304: 4cff3e7e
8308: f2b3885f
830c: a82672ff
8310: c7319f3d
8314: 8a5d8e71
8318: 2d9c4468
831c: 4e711df3
8320: 89a3ba58
8324: 6044db18
8328: 58fea466
832c: be0420e4
8330: 7557e740
8334: c6c0123c
8338: 9f0e8f18
833c: cc45d9a0
8340: 129f894e
8344: ff3f36a2
8348: eb583c09
834c: e930236e
8350: c4933887
8354: 66248ce6
8358: 2e07c7a4
835c: bbb5aba0
8360: a475fdd0
8364: 6b00dbf8
8368: 0169c068
836c: e8cc2aa2
8370: 3e7aa0b8
8374: a8565112
8378: 265fbc90
837c: ef3730cc
8380: bf9c386d
8384: 22e4e5cc
8388: 0ac1c560
838c: ff3f3744
8390: 983fdca3
8394: f14e9229
8398: fa186ea1
839c: ba739dd5
83a0: 9db2d3ea
83a4: 96090a02
83a8: 5a1978c8
83ac: e6fb0657
83b0: 3ee962d5
83b4: a362b6c8
83b8: aea396d9
83bc: 62f9f509
83c0: 984ec768
83c4: 7f401bc6
83c8: cc62dfc3
83cc: e01e309b
83d0: 1e240f12
83d4: ff3f37e7
83d8: a01aa299
83dc: a3fbba50
83e0: 3f2b9794
83e4: 135fff7d
83e8: ee5c1fc9
83ec: 882b5f4f
83f0: 4a607392
83f4: c463018f
83f8: d3a6e6e7
83fc: 1860a2e5
8400: a11077c8
8404: 77022c5f
8408: 10b1392d
840c: 8da9f4ce
8410: 5edf6c3a
8414: 344b7166
8418: 18de4c6e
841c: ff3f3888
8420: 721e1c0b
8424: 039a7a13
8428: 3f2ccd67
842c: 23377ad8
8430: cdb91857
8434: e2a3dbfd
8438: 32ef8f54
843c: df279024
8440: f876cbc4
8444: c9dcb61d
8448: 21205a96
844c: 5af4b45d
8450: dccae41f
8454: f4bfb718
8458: 5a69a734
845c: eacaeeca
8460: 161dcb0e
8464: ff3f392a
8468: d8871ced
846c: 12076544
8470: e2d6ff68
8474: df14afbf
8478: 33ad4ac9
847c: bbb03c0a
8480: 99563e3e
8484: ef033003
8488: d2c734f5
848c: 32519a9f
8490: aee9fe14
8494: cdc4b8b3
8498: b961bff1
849c: 5b2babbc
84a0: 5a5b25c3
84a4: fac7fdf5
84a8: 1175c8ba
84ac: ff3f39cd
84b0: 8c0106dc
84b4: 1b6c9a45
84b8: 0df506fe
84bc: 8cc22810
84c0: 92425606
84c4: eee8c912
84c8: 94ff8ac8
84cc: 284a3d89
84d0: a12bc1c4
84d4: 8bb6759b
84d8: 9826ea04
84dc: e77fe750
84e0: 72c36ba7
84e4: 32b635b5
84e8: feab9503
84ec: 50413188
84f0: 142f4a16
84f4: ff3f3a6e
84f8: c245deb0
84fc: 30f96bc7
8500: 12ccbeca
8504: b0fd69a8
8508: 5e253bd2
850c: 97b038e1
8510: 33bf45ed
8514: f480150b
8518: db34d74f
851c: 3031a20a
8520: d6b6923e
8524: 0889c7af
8528: 269be556
852c: 60ad24fc
8530: ec79866f
8534: c1b4cf32
8538: 14faca7c
853c: ff3f3b10
8540: 058683f8
8544: af3d6b12
8548: f66a54a1
854c: 2a499a84
8550: f2b8ade1
8554: 8a0f8109
8558: dd670385
855c: 308793ca
8560: 04ea1fb1
8564: 3f8efd6d
8568: ccd37d62
856c: 3115a96a
8570: 6218616d
8574: ef600c75
8578: 77520cce
857c: 2c2648b1
8580: 1b138d88
8584: ff3f3bb3
8588: 45993ed6
858c: 9337518f
8590: e4eeb043
8594: 88c9f024
8598: 949cf0ab
859c: e7b7cfaa
85a0: ff747842
85a4: 9bdf17cf
85a8: 65d2cdd6
85ac: 8bf01fcc
85b0: 3d1e23d7
85b4: 2c19918b
85b8: 4a9e4fb3
85bc: 6614d2a4
85c0: fcb06cf0
85c4: 684889cc
85c8: 139509ca
85cc: ff3f3c54
85d0: 98b4f87d
85d4: e7023bf8
85d8: fb5e4639
85dc: 97f4d8c1
85e0: 25d588f6
85e4: 237e778f
85e8: dd4246ae
85ec: df61ecf3
85f0: c090c5db
85f4: 896854b5
85f8: 450b0dd0
85fc: ab529dac
8600: a9ef9e1b
8604: 4f0c3d11
8608: 6ab3ee52
860c: c4cce32a
8610: 0b8145c0
8614: ff3f3cf6
8618: 0130b224
861c: fc97ae45
8620: b881a8f1
8624: b3403aa3
8628: 01f666c0
862c: 2a6e2bd9
8630: fffeffd8
8634: 9f2f9861
8638: d2a2896a
863c: f39698d6
8640: e11e70ea
8644: 37e6511b
8648: de8a4167
864c: 67a83d82
8650: 4d14a106
8654: 8c604cc5
8658: 0be005f0
865c: ff3f3d97
8660: f55cd51b
8664: 7a6e168c
8668: f38c7a3c
866c: 1bec2ea0
8670: 5ab1905d
8674: 25c6717d
8678: 20976e5c
867c: eebb897c
8680: a38c3e63
8684: 539799df
8688: 23deefbc
868c: 74abedbc
8690: 1b46548b
8694: ed322f10
8698: 421be63d
869c: f9d2d4ae
86a0: 079e03ce
86a4: ff3f3e3a
86a8: a75ffc3a
86ac: 386766f2
86b0: 7d75946c
86b4: 32912400
86b8: 8f41e434
86bc: 19f7f15c
86c0: d4446bc1
86c4: 887bc1e1
86c8: 070e6bc6
86cc: d08e952a
86d0: 27d45b82
86d4: 6916aa8d
86d8: 1ab88112
86dc: 8a1d4529
86e0: 30948385
86e4: 7dcf4ecf
86e8: 0cb9c65c
86ec: ff3f3edc
86f0: e4ff6bb4
86f4: fc3a99fa
86f8: ca1a14a4
86fc: 4d9ba378
8700: a2e7037b
8704: 46714e96
8708: b9ce7f62
870c: 32989b19
8710: 3dbded47
8714: f102ee77
8718: 3b043eff
871c: 2da3d475
8720: 4f4fe9cf
8724: 7ff4f019
8728: bf6a3d1d
872c: 61b08d26
8730: 04278212
8734: ff3f3f7e
8738: 5e326936
873c: ef5347a9
8740: 817a8e5c
8744: cfd96db8
8748: f5595ca1
874c: 7962fcb8
8750: df83e47c
8754: 2ca04b95
8758: 578074fb
875c: 4009fa2f
8760: 36758ac1
8764: 5aca12cd
8768: ed2ddc79
876c: 02ac3405
8770: a1322d6a
8774: 69f4809e
8778: 18ca4c64
877c: ff3f4020
8780: 4ec90c6c
8784: d9e37ba2
8788: 7d3535a3
878c: 0793bd7b
8790: b9859dee
8794: 40a1f78a
8798: cdc001b6
879c: 3836b150
87a0: d6bebe45
87a4: 6f40a894
87a8: 15e51f8e
87ac: cf172b7c
87b0: 9aaa840e
87b4: 4eb58e2c
87b8: 3b0e3560
87bc: c358ac8a
87c0: 124c8926
87c4: ff3f40c2
87c8: b5b64fed
87cc: b57a10bd
87d0: 7745c4b6
87d4: ab70b431
87d8: 0727d8ea
87dc: ec86a5bf
87e0: 2a2ae2a3
87e4: ca4774ef
87e8: bc95863c
87ec: 6868b01e
87f0: 781725e3
87f4: 2e50a410
87f8: c9f4c1a7
87fc: e785fcaf

//can0
[diag] $ cat /sys/kernel/debug/regmap/spi2.4/registers
0000: 4e414354
0004: 30353534
0008: 00110201
000c: 00000008
0010: 3f3f0000
0014: 1f1f0113
0018: 00000000
001c: 00000000
0020: 000100b8
0024: 0000926c
0028: 0201f31c
002c: 00000000
0800: c80004a8
0804: 00000002
0808: 00000000
080c: 00000000
0810: 00000000
0814: 00000000
0818: 00000000
081c: 00000000
0820: 00000000
0824: 00000000
0828: 00000000
082c: 00000000
0830: 8096a8ff
0834: 00000000
0838: 00000000
083c: 00000000
1000: 32150320
1004: 87654321
1008: 00000000
100c: 00800110
1010: 00000080
1014: 00000000
1018: 00000340
101c: 00001c09
1020: 000f0001
1024: 0000c017
1028: ffff0000
102c: 0000ffff
1030: 00000000
1034: 00000000
1038: 00000000
103c: 00000000
1040: 00000000
1044: 0009000f
1048: 00000300
104c: 00000000
1050: 20001800
1054: 3fffffff
1058: 00000000
105c: 00000001
1060: 00000000
1064: 00000000
1068: 00000000
106c: 00000000
1070: 00000000
1074: 00000000
1078: 00000000
107c: 00000000
1080: 00000000
1084: 00000000
1088: 00000000
108c: 00000000
1090: 1fffffff
1094: 00000000
1098: 00000000
109c: 00000000
10a0: 00400000
10a4: 00000000
10a8: 00000000
10ac: 00000000
10b0: 00001200
10b4: 00000000
10b8: 00000000
10bc: 00000777
10c0: 04001220
10c4: 00020204
10c8: 00000007
10cc: 00000000
10d0: 00000000
10d4: 00000000
10d8: 0000000f
10dc: 00000000
10e0: 00000000
10e4: 00000000
10e8: 00000000
10ec: 00000000
10f0: 00041200
10f4: 00020200
10f8: 00000001
10fc: 00000000
8000: 00000000
8004: 00000000
8008: 00000000
800c: 00000000
8010: 00000000
8014: 00000000
8018: 00000000
801c: 00000000
8020: 00000000
8024: 00000000
8028: 00000000
802c: 00000000
8030: 00000000
8034: 00000000
8038: 00000000
803c: 00000000
8040: 00000000
8044: 00000000
8048: 00000000
804c: 00000000
8050: 00000000
8054: 00000000
8058: 00000000
805c: 00000000
8060: 00000000
8064: 00000000
8068: 00000000
806c: 00000000
8070: 00000000
8074: 00000000
8078: 00000000
807c: 00000000
8080: 00000000
8084: 00000000
8088: 00000000
808c: 00000000
8090: 00000000
8094: 00000000
8098: 00000000
809c: 00000000
80a0: 00000000
80a4: 00000000
80a8: 00000000
80ac: 00000000
80b0: 00000000
80b4: 00000000
80b8: 00000000
80bc: 00000000
80c0: 00000000
80c4: 00000000
80c8: 00000000
80cc: 00000000
80d0: 00000000
80d4: 00000000
80d8: 00000000
80dc: 00000000
80e0: 00000000
80e4: 00000000
80e8: 00000000
80ec: 00000000
80f0: 00000000
80f4: 00000000
80f8: 00000000
80fc: 00000000
8100: 00000000
8104: 00000000
8108: 00000000
810c: 00000000
8110: 00000000
8114: 00000000
8118: 00000000
811c: 00000000
8120: 00000000
8124: 00000000
8128: 00000000
812c: 00000000
8130: 00000000
8134: 00000000
8138: 00000000
813c: 00000000
8140: 00000000
8144: 00000000
8148: 00000000
814c: 00000000
8150: 00000000
8154: 00000000
8158: 00000000
815c: 00000000
8160: 00000000
8164: 00000000
8168: 00000000
816c: 00000000
8170: 00000000
8174: 00000000
8178: 00000000
817c: 00000000
8180: 00000000
8184: 00000000
8188: 00000000
818c: 00000000
8190: 00000000
8194: 00000000
8198: 00000000
819c: 00000000
81a0: 00000000
81a4: 00000000
81a8: 00000000
81ac: 00000000
81b0: 00000000
81b4: 00000000
81b8: 00000000
81bc: 00000000
81c0: 00000000
81c4: 00000000
81c8: 00000000
81cc: 00000000
81d0: 00000000
81d4: 00000000
81d8: 00000000
81dc: 00000000
81e0: 00000000
81e4: 00000000
81e8: 00000000
81ec: 00000000
81f0: 00000000
81f4: 00000000
81f8: 00000000
81fc: 00000000
8200: 13000000
8204: 00bfc2bd
8208: 12140000
820c: 01bfc35e
8210: 10c40000
8214: 02bfc400
8218: 056c0000
821c: 03bfc248
8220: 13000000
8224: 00bf0000
8228: a7728093
822c: 97a0fc6b
8230: dbf61bbb
8234: 86f2691d
8238: d270997e
823c: 51220d44
8240: 64e509f4
8244: 03a8b66d
8248: f8e8689e
824c: 679ed32d
8250: 41fe8d9e
8254: 79229422
8258: caf81526
825c: 1cdba5c9
8260: 4fbc07ba
8264: dfb7a4fe
8268: 12140000
826c: 01bf0000
8270: 64c41ba8
8274: b1bd3f44
8278: 3bbcebef
827c: d37556f2
8280: a4eac5e1
8284: 620d8bba
8288: 95175aef
828c: ebf784fc
8290: 3f0f8771
8294: 8d1a7a6d
8298: fbaed013
829c: 82fb00b9
82a0: 1a2d3707
82a4: 0e06cbfa
82a8: 88bec89d
82ac: e7fa8923
82b0: 10c40000
82b4: 02bf0000
82b8: 4a65449e
82bc: f7733527
82c0: b722ed71
82c4: 969c9254
82c8: 612c512e
82cc: 3f657579
82d0: 78589078
82d4: c7bc659a
82d8: 72e1cc3e
82dc: f26b8824
82e0: eef44617
82e4: a77736d9
82e8: ac503648
82ec: 3b7da6a1
82f0: a5bf5ce5
82f4: 6922ad31
82f8: 029c0000
82fc: 03bf0000
8300: 05489d33
8304: f256ef63
8308: 6ea7067c
830c: 98e85e47
8310: e853a1ba
8314: a999388f
8318: 36784635
831c: 24cfd4f8
8320: 3bb652c6
8324: f1980678
8328: d90b9ac4
832c: e29c0ef7
8330: 78ff911e
8334: 1ce62c22
8338: 4d3a57b3
833c: a204d540
8340: 00000000
8344: 00000000
8348: 00000000
834c: 00000000
8350: 00000000
8354: 00000000
8358: 00000000
835c: 00000000
8360: 00000000
8364: 00000000
8368: 00000000
836c: 00000000
8370: 00000000
8374: 00000000
8378: 00000000
837c: 00000000
8380: 00000000
8384: 00000000
8388: 00000000
838c: 00000000
8390: 00000000
8394: 00000000
8398: 00000000
839c: 00000000
83a0: 00000000
83a4: 00000000
83a8: 00000000
83ac: 00000000
83b0: 00000000
83b4: 00000000
83b8: 00000000
83bc: 00000000
83c0: 00000000
83c4: 00000000
83c8: 00000000
83cc: 00000000
83d0: 00000000
83d4: 00000000
83d8: 00000000
83dc: 00000000
83e0: 00000000
83e4: 00000000
83e8: 00000000
83ec: 00000000
83f0: 00000000
83f4: 00000000
83f8: 00000000
83fc: 00000000
8400: 00000000
8404: 00000000
8408: 00000000
840c: 00000000
8410: 00000000
8414: 00000000
8418: 00000000
841c: 00000000
8420: 00000000
8424: 00000000
8428: 00000000
842c: 00000000
8430: 00000000
8434: 00000000
8438: 00000000
843c: 00000000
8440: 00000000
8444: 00000000
8448: 00000000
844c: 00000000
8450: 00000000
8454: 00000000
8458: 00000000
845c: 00000000
8460: 00000000
8464: 00000000
8468: 00000000
846c: 00000000
8470: 00000000
8474: 00000000
8478: 00000000
847c: 00000000
8480: 00000000
8484: 00000000
8488: 00000000
848c: 00000000
8490: 00000000
8494: 00000000
8498: 00000000
849c: 00000000
84a0: 00000000
84a4: 00000000
84a8: 00000000
84ac: 00000000
84b0: 00000000
84b4: 00000000
84b8: 00000000
84bc: 00000000
84c0: 00000000
84c4: 00000000
84c8: 00000000
84cc: 00000000
84d0: 00000000
84d4: 00000000
84d8: 00000000
84dc: 00000000
84e0: 00000000
84e4: 00000000
84e8: 00000000
84ec: 00000000
84f0: 00000000
84f4: 00000000
84f8: 00000000
84fc: 00000000
8500: 00000000
8504: 00000000
8508: 00000000
850c: 00000000
8510: 00000000
8514: 00000000
8518: 00000000
851c: 00000000
8520: 00000000
8524: 00000000
8528: 00000000
852c: 00000000
8530: 00000000
8534: 00000000
8538: 00000000
853c: 00000000
8540: 00000000
8544: 00000000
8548: 00000000
854c: 00000000
8550: 00000000
8554: 00000000
8558: 00000000
855c: 00000000
8560: 00000000
8564: 00000000
8568: 00000000
856c: 00000000
8570: 00000000
8574: 00000000
8578: 00000000
857c: 00000000
8580: 00000000
8584: 00000000
8588: 00000000
858c: 00000000
8590: 00000000
8594: 00000000
8598: 00000000
859c: 00000000
85a0: 00000000
85a4: 00000000
85a8: 00000000
85ac: 00000000
85b0: 00000000
85b4: 00000000
85b8: 00000000
85bc: 00000000
85c0: 00000000
85c4: 00000000
85c8: 00000000
85cc: 00000000
85d0: 00000000
85d4: 00000000
85d8: 00000000
85dc: 00000000
85e0: 00000000
85e4: 00000000
85e8: 00000000
85ec: 00000000
85f0: 00000000
85f4: 00000000
85f8: 00000000
85fc: 00000000
8600: 00000000
8604: 00000000
8608: 00000000
860c: 00000000
8610: 00000000
8614: 00000000
8618: 00000000
861c: 00000000
8620: 00000000
8624: 00000000
8628: 00000000
862c: 00000000
8630: 00000000
8634: 00000000
8638: 00000000
863c: 00000000
8640: 00000000
8644: 00000000
8648: 00000000
864c: 00000000
8650: 00000000
8654: 00000000
8658: 00000000
865c: 00000000
8660: 00000000
8664: 00000000
8668: 00000000
866c: 00000000
8670: 00000000
8674: 00000000
8678: 00000000
867c: 00000000
8680: 00000000
8684: 00000000
8688: 00000000
868c: 00000000
8690: 00000000
8694: 00000000
8698: 00000000
869c: 00000000
86a0: 00000000
86a4: 00000000
86a8: 00000000
86ac: 00000000
86b0: 00000000
86b4: 00000000
86b8: 00000000
86bc: 00000000
86c0: 00000000
86c4: 00000000
86c8: 00000000
86cc: 00000000
86d0: 00000000
86d4: 00000000
86d8: 00000000
86dc: 00000000
86e0: 00000000
86e4: 00000000
86e8: 00000000
86ec: 00000000
86f0: 00000000
86f4: 00000000
86f8: 00000000
86fc: 00000000
8700: 00000000
8704: 00000000
8708: 00000000
870c: 00000000
8710: 00000000
8714: 00000000
8718: 00000000
871c: 00000000
8720: 00000000
8724: 00000000
8728: 00000000
872c: 00000000
8730: 00000000
8734: 00000000
8738: 00000000
873c: 00000000
8740: 00000000
8744: 00000000
8748: 00000000
874c: 00000000
8750: 00000000
8754: 00000000
8758: 00000000
875c: 00000000
8760: 00000000
8764: 00000000
8768: 00000000
876c: 00000000
8770: 00000000
8774: 00000000
8778: 00000000
877c: 00000000
8780: 00000000
8784: 00000000
8788: 00000000
878c: 00000000
8790: 00000000
8794: 00000000
8798: 00000000
879c: 00000000
87a0: 00000000
87a4: 00000000
87a8: 00000000
87ac: 00000000
87b0: 00000000
87b4: 00000000
87b8: 00000000
87bc: 00000000
87c0: 00000000
87c4: 00000000
87c8: 00000000
87cc: 00000000
87d0: 00000000
87d4: 00000000
87d8: 00000000
87dc: 00000000
87e0: 00000000
87e4: 00000000
87e8: 00000000
87ec: 00000000
87f0: 00000000
87f4: 00000000
87f8: 00000000
87fc: 00000000

Please find dump of device registers.

0 Jonathan Nerger 21 days ago in reply to Himanshu Gupta

TI__Mastermind 37941 points

Hello Himanshu,

Thanks for the register dump.

I can see a couple of issues. The first is with the interrupt register 0x1050 which has bits 0, 2, and 3 set. These are related to the RX FIFO and has the RF0N bit which is for new messages, RF0F bit which is set when the RX FIFO 0 is full, and the RF0L bit is set when a message is received while the FIFO is full resulting in the loss of that message.

Your RX FIFO 0 configuration is set to Blocking Mode (0x10A0[31]) so new messages are blocked from being stored when the RX FIFO is full. This is why the receive counter is not incrementing.

The MCU should be reading the messages out of the RX FIFO based on the Put and Get Index values in the RX FIFO 0 Status register (0x10A4) and then acknowledging they have been read by writing the index number to the RX FIFO 0 Acknowledge register 0x10A8) which will release the RX FIFO Element to be used again.

If the messages arrive faster than the MCU can read and acknowledge the messages, then eventually the FIFO will become full and message data will be lost.

The second issue I see is that your configuration exceeds the maximum amount of MRAM in the device which will cause issues. The memory cell index wraps around if a location greater than the max cell is addressed which can cause other elements in your MRAM to be overwritten.

The TCAN4550 only has 2k of MRAM, and your configuration has 64 RX FIFO 0 elements with the maximum 64 byte data fields allocated. Then you have an additional 4 TX buffer elements with the maximum 64 byte data field allocated as well as 4 TX Event FIFO elements.

Note that the MCAN IP which was developed by Bosch and licensed to use within the TCAN4550 can support applications with much greater MRAM memory blocks. However, the TCAN4550 only has 2k so your allocation must be less than 2048 bytes. The MRAM address range is 0x8000 to 0x87FF.

For example, a write or read to address 0x8800 will wrap around and access cell 0x8000 making it possible to overwrite and corrupt the entire configuration resulting in run tome errors.

Please reduce the number of RX FIFO 0 elements so that your configuration is less than 2048 bytes. My calculations show that with 4 TX Buffer elements and 4 TX Event FIFO elements, you might be able to support 24 RX FIFO buffer elements without exceeding 2048 total bytes. Please verify.

Regards,

Jonathan

0 Himanshu Gupta 20 days ago in reply to Jonathan Nerger

Prodigy 30 points

Hello Jonathan,

Thanks for the quick feedback, please find inline response:-

The first is with the interrupt register 0x1050 which has bits 0, 2, and 3 set. These are related to the RX FIFO and has the RF0N bit which is for new messages, RF0F bit which is set when the RX FIFO 0 is full, and the RF0L bit is set when a message is received while the FIFO is full resulting in the loss of that message.

-> We have configured the setup with CAN FD on 500 FPS as per data sheet 8Mbps support is there for CAN FD.
500FPS = 500*600 = 300000 bps => 300Kbps

Can you suggest on which Rate it should run to avoid overflow and also what is meaning of 8Mbps data rate.

Your RX FIFO 0 configuration is set to Blocking Mode (0x10A0[31]) so new messages are blocked from being stored when the RX FIFO is full. This is why the receive counter is not incrementing.
The MCU should be reading the messages out of the RX FIFO based on the Put and Get Index values in the RX FIFO 0 Status register (0x10A4) and then acknowledging they have been read by writing the index number to the RX FIFO 0 Acknowledge register 0x10A8) which will release the RX FIFO Element to be used again.

-> m_can driver already taking care of it with SPI core, can you suggest any modification to opensource m_can driver for 5.15 Kernel version to drain FIFO fast.

If the messages arrive faster than the MCU can read and acknowledge the messages, then eventually the FIFO will become full and message data will be lost.
The second issue I see is that your configuration exceeds the maximum amount of MRAM in the device which will cause issues. The memory cell index wraps around if a location greater than the max cell is addressed which can cause other elements in your MRAM to be overwritten.
The TCAN4550 only has 2k of MRAM, and your configuration has 64 RX FIFO 0 elements with the maximum 64 byte data fields allocated. Then you have an additional 4 TX buffer elements with the maximum 64 byte data field allocated as well as 4 TX Event FIFO elements.
Note that the MCAN IP which was developed by Bosch and licensed to use within the TCAN4550 can support applications with much greater MRAM memory blocks. However, the TCAN4550 only has 2k so your allocation must be less than 2048 bytes. The MRAM address range is 0x8000 to 0x87FF.
For example, a write or read to address 0x8800 will wrap around and access cell 0x8000 making it possible to overwrite and corrupt the entire configuration resulting in run tome errors.
Please reduce the number of RX FIFO 0 elements so that your configuration is less than 2048 bytes. My calculations show that with 4 TX Buffer elements and 4 TX Event FIFO elements, you might be able to support 24 RX FIFO buffer elements without exceeding 2048 total bytes. Please verify.

-> yes, you are right we just checking multiple combination of MRAM registers.
Our current cnfig for bosch,mram-cfg = <0x0 0 0 20 0 0 4 4>;
still issue persist.

0 Jonathan Nerger 20 days ago in reply to Himanshu Gupta

TI__Mastermind 37941 points

Hello Himanshu,

All communication with the TCAN4550 occurs through the SPI interface, and this is the limiting factor.

All TX and RX message data must be transferred to and from the MRAM buffers through SPI, and all registers that need to be read and written to also must use the same SPI interface. The time needed to accomplish all of this SPI communication determines the overall processing time required to transmit or receive a single CAN FD message.

The maximum bit rate that can be used during the Data Phase of a CAN FD message is 8Mbps but this only reduces the time the CAN bus is occupied with that message, but it has no impact on the process time needed to transfer that message to or from the MCU through the SPI interface.

In other words, the SPI processing time is the same for a message that is transmitted with a CAN Data Bit Rate of 1Mbps or 8Mbps.

If the CAN messages are received at an interval that is faster than the SPI processing time, the RX FIFO will eventually overflow.

Regards,

Jonathan

Interface

Interface forum

TCAN4550: CAN interface stops receiving frames after some time

Setup:

Device Tree Configuration:

CAN Interface configuration:

Current Test Method

Logs:

Observations: