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DS90UB921-Q1: DS90UB921-Q1: Custom board design guidance for 16-bit parallel FPGA source (no EVM)

Hetvi Patel
Prodigy 30 points

Part Number: DS90UB921-Q1
Other Parts Discussed in Thread: DS90UB926Q-Q1

Hello,

I have the DS90UB921-Q1 serializer and DS90UB926QSQX/NOPB deserializer as bare ICs (no EVM) and am designing a custom board around them. My source is an FPGA driving a 16-bit parallel bus at approximately 75 MHz over about 1 m of cable. This is my first FPD-Link III design.

Three questions before I fabricate:

1) My source is 16-bit but the DS90UB921-Q1 has 24 data inputs. How should the 8 unused DIN pins be terminated, and is there a preferred bit mapping when using fewer than 24 bits?

2) Without an EVM I must configure both devices from my own I2C master. What is the minimum strap resistor configuration needed to bring the DS90UB921-Q1 and DS90UB926Q-Q1 up in a basic working mode, and what is the required power-up and PDB release sequencing?

3) What are the setup and hold requirements on the parallel data bus relative to PCLK, and is the sampling edge selected by strap pin or by I2C register?

4)

  • Are there any registers whose default (strap) values must match between 921 and 926, or does the link handle mismatch gracefully?
  • Does the 921 need any indication that a deserializer is present, or does it transmit blindly regardless?

If there is a schematic checklist or bring-up guide for a first custom FPD-Link III design, a pointer would be appreciated. In particular, what should I check first if the DS90UB926Q-Q1 LOCK pin never asserts?

Thank you,
Hetvi

  • 0
    TI__Genius 13726 points

    Hi Hetvi,

    Hetvi Patel said:
    My source is 16-bit but the DS90UB921-Q1 has 24 data inputs. How should the 8 unused DIN pins be terminated, and is there a preferred bit mapping when using fewer than 24 bits?

    Here is another good thread that addresses this question:

    Hetvi Patel said:
    2) Without an EVM I must configure both devices from my own I2C master. What is the minimum strap resistor configuration needed to bring the DS90UB921-Q1 and DS90UB926Q-Q1 up in a basic working mode, and what is the required power-up and PDB release sequencing?

    The power sequencing requirements for each device can be found in the "Power Supply Recommendations" sections of their datasheets. It is important to note as well that the deserializer should be powered on after the serializer.

    As far as which MODE_SEL resistor configurations are needed, this will depend on your architecture and system needs. Additional details can be found in the "Configuration Select (MODE_SEL)" section of the datasheets.

    Hetvi Patel said:
    What are the setup and hold requirements on the parallel data bus relative to PCLK, and is the sampling edge selected by strap pin or by I2C register?

    I'm not sure I understand the question. Do you mean what the setup and hold times for I2C are for the device? If so, here are the I2C specs from the 921 datasheet:

    There are other various registers that can change the I2C settings from default, including registers 0x3, 0x5, 0x6, 0x7, 0x8, 0x17, 0x18, and 0x19.

    Hetvi Patel said:
    • Are there any registers whose default (strap) values must match between 921 and 926, or does the link handle mismatch gracefully?
    • Does the 921 need any indication that a deserializer is present, or does it transmit blindly regardless?

    I believe the only strap that matters for these devices to work together is that the 926 "BACKWARD COMPATIBLE" field for it's MODE_SEL must be low since the 921 is the same generation (DS90Ux92x-Q1).

    The 921 will attempt to transmit by default if a PCLK is being applied to the input of the serializer. 

    Hetvi Patel said:
    If there is a schematic checklist or bring-up guide for a first custom FPD-Link III design, a pointer would be appreciated. In particular, what should I check first if the DS90UB926Q-Q1 LOCK pin never asserts?

    The EVM user guide would be a good place to start, it has info on initial bring up and some PCB design examples/recommendations:

    As far as debugging an issue where the DES lock pin never asserts, this is typically done on a case by case basis; however, this usually means there is an issue with the video being sent by the SoC and what the devices are expecting based on their straps and configuration. The first step is usually to get a register dump of the SER and DES, and to see how often the issue occurs. If you run into an issue like that, we can help troubleshoot the cause, but this is done on a case by case basis.

    Please let me know if you have any other questions.

    BR,

    Cameron