AM3352: Query Regarding the BOOT MODE SEQUENCE AND GPMC

Hello Krishan,

There is a very important pin muxing conflict you must be aware of, which is directly relevant to you NAND → NANDI2C → MMC0 → UART0 configuration as well:

"If MMC1 is used, the GPMC interface is not usable, due to pin muxing options." — this is from the AM335x TRM section 26.1.8.5.2 System Interconnection.

Since you are using GPMC with an 8-bit NAND and MMC0 (SD card) as the fallback,your chosen configuration of

NAND → NANDI2C → MMC0 → UART0 is fully compatible — because MMC1 is not in this sequence.

However, for the MMC1 → MMC0 → UART0 → USB0 configuration being considered: since MMC1 and GPMC share pins, you cannot have NAND (GPMC) and MMC1 in the same design simultaneously. If you select a SYSBOOT value that includes both NAND and MMC1 in the device list, you would need to ensure the GPMC pins are not driven in a conflicting way when the ROM attempts MMC1 boot.

Krishan Arora said:

1. MMC1 → MMC0 Boot Sequence

The boot ROM will automatically recover and proceed to MMC0 if MMC1 fails. The boot process will not get permanently stuck at MMC1.

The boot ROM follows a sequential booting procedure. For each device in the configured boot list, it executes one of two procedures: memory booting (for NOR, NAND, MMC, SPI-EEPROM) or peripheral booting (for UART, USB, Ethernet).

For MMC specifically, the ROM goes through an Initialization and Detection phase (you can review in the AM335x TRM in section 26.1.8.5.4 Initialization and Detection):

1. The ROM first sends CMD1 to the MMC1 interface. This command is only acknowledged by MMC-type devices.
2. If no response is received, the ROM then sends ACMD41 (CMD55 + ACMD41), which is specific to SD devices.
3. If no response is received to either CMD1 or ACMD41, the ROM concludes that no device is connected and exits the MMC/SD boot procedure with a FAIL result.
4. Upon this FAIL, the ROM moves on to the next device in the boot list — in your sequence, that would be MMC0.

If neither memory device nor card is detected then the ROM Code carries on to the next booting device.

While the ROM will eventually move on, the detection process is not instantaneous. The boot ROM will:

• Issue CMD1, wait for a response (with a data timeout, MMCHS_SYSCTL[DTO]), and if no response is received, generate a

MMCHS_STAT[DTO] (Data Timeout) event.

• Then try ACMD41, with another timeout cycle.

In the AM335x Hardware Design Guide (AM335x Hardware Design Guide) in section 3 Selecting the Boot Mode it is stated:

"Keep in mind that some boot sources take some time to timeout if that boot source is not available."

The boot will not get stuck indefinitely, but there will be a measurable delay at the MMC1 stage before the ROM advances to MMC0. This delay is governed by the data timeout counter (MMCHS_SYSCTL[DTO]).

Krishan Arora said:

2. NAND → NANDI2C → MMC0 → UART0 Boot Sequence

The same fallback behavior applies. If NAND is blank or unprogrammed, the boot ROM will automatically detect the failure, exit the NAND boot procedure, and proceed to NANDI2C, then MMC0, then UART0. The boot process will not get stuck on a blank NAND.

The NAND boot procedure is a memory booting type, which follows a structured sequence of steps before attempting to load a boot image. You can review in the AM335x TRM in section 26.1.8.4.2 Initialization and Detection.

This general fallback behavior is confirmed explicitly by the AM335x Hardware Design Guide in section 3. Selecting the Boot Mode:

"If the first boot source fails to boot, the ROM will move on to the next one in the sequence."

And from the AM335x TRM in section 21.6.7 SYSBOOT Configuration Pins:

"The device will drive EMAC, GPMC, SPI and I2C pins, in that order, depending on which boot device finally succeeds."

The failure mode for a blank NAND is subtly different from a completely absent device, and this has an important implication:

• NAND physically present but blank (0xFF)- ROM detects the device (READ ID succeeds), reads page 0, finds no valid TOC → FAIL → advances quickly
• NAND physically absent / no device on bus- ROM may receive no response or garbage data on the GPMC bus → FAIL → advances, but bus contention risk (see below)

In either case, the ROM advances. However, the blank NAND case is actually cleaner — the device acknowledges commands and simply returns erased (0xFF) data with no valid image signature.

Krishan Arora said:

3. NANDI2C / I2C0 Configuration

The absence of a boot EEPROM on I2C0 will NOT cause the boot process to get stuck. The boot ROM will attempt the NANDI2C stage, fail to get a valid response from the expected EEPROM address, time out, and then automatically proceed to MMC0. This is the same universal fallback behavior confirmed throughout this discussion.

From the AM335x TRM in section 26.1.8.4.2 Initialization and Detection in the topic Reading NAND Geometry From I2C EEPROM:

"If this boot mode is selected, the ROM code tries to read NAND geometry from an I2C EEPROM. If the read is successful, ROM code then proceeds to next steps of NAND boot."

The ROM performs the following specific I2C transaction:

• Accesses I2C slave address 0x50 (standard EEPROM address).
• Sends a 2-byte address (0x0080) to perform a selective read.
• Reads 7 bytes starting at offset 0x80.
• Checks for a 4-byte magic number sequence: 0x10, 0xB3, 0x57, 0xA6 at bytes 0x80–0x83

If the ROM receives no ACK from address 0x50 (because no EEPROM is present), or if it receives data that does not match the expected magic number, the NANDI2C boot stage returns FAIL, and the ROM advances to the next device in the boot list, which in your case is MMC0.

The only pins driven during this stage are i2c0_scl and i2c0_sda (Table 26-16 Pins Used for NANDI2C Boot for I2C EEPROM Access of the AM335x TRM).

You have the PMIC connected to I2C0. The boot ROM will:

1. Drive i2c0_scl and i2c0_sda.
2. Issue an I2C START condition and transmit a byte to slave address 0x50.
3. Wait for an ACK.

The PMIC is highly unlikely to be at I2C address 0x50, so the ROM will receive a NACK and move on. However, you must verify these things:

• PMIC I2C address- If your PMIC happens to be addressable at 0x50, the ROM's read command could inadvertently issue unexpected I2C transactions to it. Verify your PMIC's I2C address range.
• I2C bus state during boot- Ensure the PMIC does not require the I2C bus to be in a specific state at power-up. The ROM will drive SCL/SDA, which could interfere with PMIC initialization if timing is critical.
• I2C pull-up voltage- Ensure i2c0_scl and i2c0_sda are pulled up to the correct I/O voltage per the AM335x datasheet ball characteristics table.

In the AM335x TRM in section 26.1.6.2.1 SYSBOOT Configuration Pins is stated:

"Ensure that if a specific boot mode in the sequence chosen is not used, the components using those particular signals do not conflict with the ROM driving those signals."

What you could do is to confirm your PMIC's 7-bit I2C address is not 0x50. If it is, consider selecting a SYSBOOT configuration that does not include NANDI2C in the boot sequence, so the I2C0 bus is not driven by the ROM during boot.

In the AM335x Hardware Design Guide in section 3. Selecting the Boot Mode it is stated:

"If the first boot source fails to boot, the ROM will move on to the next one in the sequence."

This is confirmed universally across all boot sources. Your boot sequence NAND → NANDI2C → MMC0 → UART0 will reliably fall through to MMC0 as long as:

• NAND is blank or has no valid boot image (TOC not found)
• NANDI2C fails (no EEPROM at 0x50 responding with valid magic number)
• MMC0 has a valid, properly formatted boot image (MLO + u-boot or equivalent)

Krishan Arora said:

QUE2: I want to use GPMC in which i want to connect NOR FLASH, what is the Maximum size of NOR flash i can use?

From the AM335x TRM in section 7.1.4.2.6 GPMC Features and Settings:

• Maximum GPMC addressing capability: 512 MBytes divided into eight chip-selects.
• Maximum supported memory size: 256 MBytes (must be a power-of-2).
• Minimum supported memory size: 16 MBytes (must be a power-of-2). Aliasing occurs when addressing smaller memories.

Best Regards,

Borislav Lazarkov