DP83825I: RMII lengths and impedance

Part Number: DP83825I
Other Parts Discussed in Thread: DP83848Q-Q1

There appears to be a lot of conflicting information between vendors, forums, and blogs about the considerations for running short RMII traces. I think some of the confusion might be about why some of these things are done, how much is RMII and how much is specific to a specific PHY.

For b ackground, I'm connecting the DP83825I to an STM32 microcontroller with integrated MAC. The crystal is configured for RMII Leader Signaling and all RMII traces are less than 1.5cm.

The DP83825I datasheet says

  • "Traces must be routed with 50-ohm impedance to ground[...] Impedance discontinuities cause reflections, leading to emissions and signal integrity issues."
  • "Keep trace lengths as short as possible"
  • "All RMII transmit signal trace lengths must match each other, and all RMII receive signal trace lengths must match each other, too."

The RMII specification says:

  • "All connections are intended to be point-to-point connections on PCBs. Typically these connections can be treated as electrically short paths and transmission line reflections can be safely ignored."
  • The RMII specification describes how the signals are synchronous with the clock, which would suggest that length matching would be relative to the minimum hold time, which for the DP83825I is 2ns for TX and 4ns for RX.

I'm missing something in trying to reconcile these two understandings. This opens a few questions.

1) Why are TX signal traces supposed to be length matched together, and RX signal traces are supposed to be length-matched together, and nothing is supposed to be length-matched to the REF_CLK? Do you have some circuitry that calibrates to account for length differences separately in the TX and RX registers? Is it that within your 6-inch recommended maximum length the length differences shouldn't matter? But then why would TX and RX need to match?

2) When you say the "TX signal traces" need to match, does that include TX_EN? Since TX_EN is also synchronous with REF_CLK, I would guess the answer is, yes.

3) Similarly, when you say "RX signal traces," does that include for CRV_RX? Since CRV_RX is also synchronous with REF_CLK for nibble-aligned start and end signaling, I would guess the answer is also yes.

4) You recommend 2-6 inches for signal lengths, but you also recommend "short as possible." Are there concerns different requirements we should be considering for cases when trace lengths are less than 2 inches?

5) Why do you still require 50-ohm impedance matching below the critcal length?

Thank you.

  • Hi Jared,

    1. Similar to this E2E RMII traces should all match to the reference clock.

    2. Yes this includes TX_EN

    3. Yes this includes CRS_DV

    4. Trace lengths under 2" are ok. Having a very short trace length can make component placement difficult. How short of a trace are you planning to use?

    5. Impedance matching minimizes signal reflections caused from impedance discontinuity. Signal reflections are not great for signal quality or EMI emissions.

    Best,

    Shan

  • Thank you!

    1) I saw that other thread, though they appear to be using RMII Follower Signaling with the DP83848Q-Q1. In the DP83825I datasheet, the language splitting out the TX and RX sides plus no mention of length matching to REF_CLK was a little confusing. So it sounds like the DP83825I isn't doing any special calibration in that regard?

    2 & 3) That makes sense.

    4) I drafted a design for a tight space. The way the pins lined up, the TX/REF_CLK traces were 9mm and the RX traces were 3mm. So if there is some kind of lower bound where chips are too short, that would be useful to know.

    5) I hear that, and can accept that as common practice. For now, I'm one of a confused multitude who can't see how the guidance reconciles with physics, but I though I'd ask in case there was a factor I wasn't considering.

  • Hi Jared,

    1) This is correct. In RMII, it is important to length match to ref clock as the bus signals are intended to be synchronous to that clock.

    4) There is no lower bound I am aware of.

    Sincerely,

    Gerome