Part Number: DP83826I
Dear TI Support,
I have a question regarding the MII TX_CLK timing of the DP83826I.
According to the DP83826I datasheet (Rev. I), the 100BASE-TX MII timing specifications are:
* TX_CLK High Time: 16 ns min, 24 ns max
* TX_CLK Low Time: 16 ns min, 24 ns max
* TX_D[3:0], TX_EN, TX_ER Setup to TX_CLK: 10 ns min
* TX_D[3:0], TX_EN, TX_ER Hold from TX_CLK: 0 ns min
However, I could not find a specification for the minimum TX_CLK period in the MII TX timing table.
If the minimum high and low times are considered independently:
16 ns + 16 ns = 32 ns
This appears to allow a TX_CLK frequency higher than 25 MHz (period shorter than 40 ns).
Could you please clarify the following?
1. What is the guaranteed minimum TX_CLK period in 100-Mbps MII mode?
2. Should the 16 ns minimum high and low times be interpreted independently, or is there an additional constraint on the total TX_CLK period?
3. Is the MII TX_CLK frequency/period guaranteed to comply with the 25-MHz MII timing requirements specified by IEEE 802.3?
If possible, could you please provide the guaranteed minimum TX_CLK period, or clarify how the TX_CLK high/low time specifications should be interpreted?
Thank you for your support.
