DP83TC817S-Q1: Request for DP83TC817S-Q1 Bootstrap / Strap Configuration Documentation

Part Number: DP83TC817S-Q1
Other Parts Discussed in Thread: DP83TC817EVM-MC, TIDA-020072

Hello,

I am currently designing a system using the DP83TC817S-Q1 connected through SGMII to a Microchip LAN96455F Ethernet switch.

I need the complete documentation for the DP83TC817S-Q1 bootstrap / strap configuration, especially the parts that are not included in the public short datasheet.

Could you please provide the full documentation covering the following items:

• Complete bootstrap / strap configuration tables
• Exact resistor values / voltage levels required for each strap mode
• PHY address selection using strap pins
• Mapping of the strap pins, especially:
  • RX_CTRL
  • RX_ER
  • RX_CLK
  • GPIO_3
  • and any other pins involved in bootstrap configuration
• List of all PHY addresses that can be selected by hardware straps
• Confirmation whether PHY address 0x02 can be selected directly by straps
• Exact configuration required to force:
  • SGMII MAC interface
  • PHY address 0x02
• Register or status bits that allow verification of the latched strap configuration after reset, for example:
  • SOR_VECTOR
  • CHIP_SOR
  • or equivalent registers
• Description of when the strap values are sampled relative to RESET
• Internal pull-up / pull-down values or ranges for the strap pins
• Any restrictions regarding external pull-up / pull-down resistor values
• Default strap configuration of the DP83TC817EVM-MC
• The complete DP83TC817EVM-MC User's Guide, if it contains these tables
• The full DP83TC817S-Q1 datasheet / register documentation, if additional information is available under NDA or through TI MySecureSoftware

The reason this information is important is that the LAN96455F, when operating in unmanaged mode, expects the external PHY connected to SGMII0 to respond at MDIO address 0x02.

Our current DP83TC817S-Q1 hardware is based closely on the TI TIDA-020072 reference design, where the DP83TC817S-Q1 appears to use PHY address 0x0F.

We therefore need to determine whether the DP83TC817S-Q1 can be configured by hardware straps to address 0x02, or whether this requires register programming after reset.

Please also confirm whether the following architecture is fully supported:

LAN96455F SGMII0

        |

        | SGMII

        |

DP83TC817S-Q1

PHY address = 0x02

If address 0x02 cannot be selected by straps, please advise the recommended method for using DP83TC817S-Q1 with a MAC/switch that requires PHY address 0x02 during autonomous boot.

Thank you in advance for your support.

My Best Regards,

-- 

Ioannis Mourtsiadis