Part Number: SN65DSI84-Q1
Hi team,
The customer's current design uses the DSI clock as the reference clock for the SN65DSI84-Q1. We would like to know the specific jitter requirements for the DSI clock in this configuration.
My understanding is that when using the DSI clock, the key considerations are ensuring the clock frequency is between 40 MHz to 500 MHz, configuring the clock lane for HS Continuous Mode, and meeting the setup and hold time requirements for the data lanes relative to the clock lane.
Are there any other jitter-related constraints or requirements?
