TUSB320LAI: OUT1 maximum latency after attached-source Rp downgrade

Part Number: TUSB320LAI
Other Parts Discussed in Thread: TPS709,

Hi Experts,

Can you help with the inquiry below?

We are designing five USB-only ESP32-S3 optical-acquisition prototypes, requiring a data-capable Type-C host/hub advertising at least 1.5 A. Wi-Fi is unsupported, BLE deferred, and all battery/charging components are unpopulated. No boards have been routed or ordered.

TUSB320LAIRWBR is a fixed sink in GPIO mode, with I2C disabled. Hardware interprets OUT1 to allow the main feed for 1.5 A or 3 A advertisement and inhibit default-current/unattached operation. No MCU bypass or firmware negotiation is present. TPS709 supplies 3.3 V; a valid-VBUS supervisor delays controller enable and an independent 3.0 V AON supervisor clamps eFuse enable during invalid supply. A 470 ohm bleeder discharges the 10 uF AON output after removal.

TI discussion 1453788 (TUSB320LAI current-mode update after CCx voltage changes) establishes dynamic update support but does not provide the worst-case OUT1 GPIO latency needed here. Please confirm for this exact LAI version:

1. Guaranteed maximum delay from an established-attach CC transition 1.5 A to default or 3 A to default to OUT1 withdrawing high-current permission, across VDD 2.7–3.465 V and TA -40 to 85 C. Define threshold/dwell, filtering and output-load conditions. Include detach with VBUS remaining high.
2. OUT1 state/drive and any transient permission during VDD ramp, below UVLO, POR and restart with VBUS already present. What VDD ramp/discharge duration guarantees a new valid state? Is an external pull/clamp sufficient?
3. Behavior for 3 A to 1.5 A (continued permission), brief threshold crossings/contact bounce and changing Rp without dropping VBUS. Can GPIO remain stale or latched until an I2C read/reset? Please distinguish initial-attach debounce from established-attach downgrade timing.
4. Applicable reference circuit or compliance timing requirements for our hardware qualification path before operation above default current.

Please distinguish guaranteed limits from typical/characterized data and provide document/revision references or a suitable pre-layout evaluation procedure. We can revise hardware before layout and do not intend to rely on undocumented timing. No attachments or manufacturing authorization are included.

Regards,

Marvin