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SN65DSI86: Inquiry Regarding the Usage of SN65DSI86

Kyohei
Genius 3141 points

Part Number: SN65DSI86

My customer is currently evaluating NXP's processor, the MIMX8QP5CVUFFAB, and would like to inquire about TI's DSI-to-DisplayPort bridge device, SN65DSI86.
 
 
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• J9 is described as a DisplayPort connector with a "(Default)" notation.
Is it correct to assume that video output can be displayed on any monitor equipped with a DisplayPort connector?
 
• Do you have any recommendations for a suitable DSI signal source to be used with the SN65DSI86?
This could be an evaluation board, a signal generator, or any other appropriate solution.
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We appreciate your support and look forward to your response.
Best regards,
Kyohei
  • 0
    TI__Genius 13306 points

    Hi Kyohei-san,

    Kyohei said:
    J9 is described as a DisplayPort connector with a "(Default)" notation.
    Is it correct to assume that video output can be displayed on any monitor equipped with a DisplayPort connector?

    Correct, so long as the monitor supports eDP mode, you can plug it into a traditional consumer monitor. This will also depend on the video timings that are being send via DSI, but in general you are correct.

    Kyohei said:
    Do you have any recommendations for a suitable DSI signal source to be used with the SN65DSI86?
    This could be an evaluation board, a signal generator, or any other appropriate solution.

    Unfortunately we do not have a great recommendation for a DSI source outside of using an SoC. I know that TI's TDA4 SoC has a DSI interface included, but I haven't personally used it before.

    BR,

    Cameron

  • 0 in reply to Cameron Hoholik-Carlson
    Genius 3141 points

    Hi Cameron-san,

    Thank you for your support.

    I have additional questions.

    Regarding the I2C over AUX function of the SN65DSI86:

    1. Is my understanding correct that AUX control functions, such as EDID readout, can be performed through the SCL (pin H1) and SDA (pin J1) signals described as the Local I2C interface?

    2. If the above understanding is correct, is it also correct that the host can negotiate display parameters such as resolution and refresh rate via the Local I2C interface, and then the SN65DSI86 can convert the incoming video data from the DSI interface and output it through the DisplayPort interface?

    Best regards,

    Kyohei

  • 0 in reply to Kyohei
    TI__Mastermind 31820 points

    Hi Kyohei,

    1. Yes, using the direct method for reading EDID, the host can read the EDID using using the device local I2C by using the I2C-over-aux.

    2. The DSI86 needs to be programmed with the display timings which match the panel display, and in turn this will also be matched by the incoming DSI input.

    Reading EDID:

    So, if EDID needs to be read, then the host can use the I2C over AUX to read the EDID, to then program the DSI86, and send MIPI DSI video with the same timings. The DSI86, with these programmed timings, can process the incoming DSI video and convert to DP output.

    The EDID reading is used to communicate what timings the display can support. So this is not a negotiation, but reading the panel EDID timings. However, some panels may advertise multiple timings with EDID and then the host/SoC can decide which timings to use.

    Known timings:

    If the display timings are known, and you intend to use this with specific panels, you could also simply find either the EDID or panel datasheet to find the timings. Then have the host send MIPI DSI video of those timings, and program the DSI86 for that specific resolution. This would also skip the EDID reading step since the timings are already known.

    Application questions:
    Could you tell us more about what you are trying to test or what system you are trying to design?

    As a source, you could use a DSI generator, the SoC/processor that the customer intends to use, or even Raspberry Pi that can support the video input mentioned in the datasheet: 
    "Implements MIPI® D-PHY version 1.1 physical layer front-end and display serial interface (DSI) version 1.02.00"

    If you know what processor is to be used in the system, you could also use that EVK directly with this DSI86 EVM.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Genius 3141 points

    Hi Ikram-san,

    Thank you for your previous response.

    We have some additional questions regarding HPD/IRQ handling and Linux driver support.

    Our proposed configuration is as follows:

    NXP i.MX8M Plus → MIPI DSI → SN65DSI86 → DP path → external DisplayPort sink

    The DP path may include the TUSB546A and a USB Type-C DisplayPort Alt Mode interface.

    Could you please confirm the following points from the SN65DSI86 perspective?

    1. HPD and IRQ handling

    When the SN65DSI86 detects an HPD event from the DP sink, can the HPD event or related status change be reported to the host processor through the SN65DSI86 IRQ pin?

    If yes, could you please identify the interrupt/status register and register bits that the host should monitor and clear?

    We plan to connect the SN65DSI86 IRQ pin to an interrupt-capable GPIO on the i.MX8M Plus. We understand that the GPIO and interrupt-controller configuration is specific to the NXP processor.

    2. Linux driver support

    We found the upstream Linux DRM bridge driver:

    drivers/gpu/drm/bridge/ti-sn65dsi86.c

    Could you please confirm the following?

    1. Does this driver support HPD event handling through the SN65DSI86 IRQ pin?
    2. Does this driver support EDID reading through the SN65DSI86 AUX channel?
    3. Does this driver perform DP link training and configure the SN65DSI86 according to the display mode selected by Linux DRM?
    4. Is this driver officially supported or maintained by TI, or is it maintained only by the upstream Linux community?
    5. Are any additional TI-specific modifications required when using this driver with an NXP i.MX8M Plus BSP?

    3. External DisplayPort and DP Alt Mode connection

    The SN65DSI86 is described as a MIPI DSI-to-eDP bridge. In our application, its DP output may be connected to an external DP sink through the TUSB546A and a USB Type-C DP Alt Mode path.

    From the SN65DSI86 perspective, are there any restrictions or concerns regarding the following operations?

    • HPD propagation from the external DP sink
    • EDID reading through AUX
    • Hot-plug and reconnection
    • DP link training after cable connection
    • Operation through the TUSB546A signal path

    We understand that the NXP processor, TUSB546A, USB PD controller, and the complete USB Type-C system must be checked separately. Therefore, we would appreciate your confirmation specifically regarding the capabilities and limitations of the SN65DSI86.

    If possible, please provide a Yes/No answer for each item and indicate any required hardware connections, register settings, software requirements, or limitations.

    Best regards,

    Kyohei

  • 0 in reply to Kyohei
    TI__Mastermind 31820 points

    Hi Kyohei, please give me 1-2 days to look into this and get back to you about the options and resources for DP Alt mode.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Genius 3141 points
    Thank you for letting me know. I understand that the confirmation will take one to two days. I would appreciate it if you could proceed with the investigation.
  • 0 in reply to Kyohei
    TI__Mastermind 31820 points

    Hi Kyohei,

    I added our responses inline to your questions below:

    1. HPD and IRQ handling

    When the SN65DSI86 detects an HPD event from the DP sink, can the HPD event or related status change be reported to the host processor through the SN65DSI86 IRQ pin?

    Yes, this should be supported. The datasheet states: "The DSIx6 supports assertion of IRQ for HPD events. When an IRQ_HPD event is detected and both IRQ_EN and IRQ_HPD_EN bits are set, then the DSIx6 will assert the IRQ."

    If yes, could you please identify the interrupt/status register and register bits that the host should monitor and clear?

    Both IRQ_EN (register 0xE0[0]) and IRQ_HPD_EN (register 0xE6[0]) should be set.

    We plan to connect the SN65DSI86 IRQ pin to an interrupt-capable GPIO on the i.MX8M Plus. We understand that the GPIO and interrupt-controller configuration is specific to the NXP processor.

    These are register settings. So please add these settings to the initialization config so the registers are set via I2C.

    2. Linux driver support

    We found the upstream Linux DRM bridge driver:

    drivers/gpu/drm/bridge/ti-sn65dsi86.c

    Could you please share where you found this? The only driver we have for reference is shared in the link below. The scripts are shared as-is and we are not updating or supporting further.

    E2E thread: [FAQ] SN65DSI8x Programming Tools
    Link to Linux driver code: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/video/omap2/dss/dsi.c?id=c16fa4f2ad19908a47c63d8fa436a1178438c7e7

    Could you please confirm the following?

    1. Does this driver support HPD event handling through the SN65DSI86 IRQ pin?
    2. Does this driver support EDID reading through the SN65DSI86 AUX channel?
    3. Does this driver perform DP link training and configure the SN65DSI86 according to the display mode selected by Linux DRM?
    4. Is this driver officially supported or maintained by TI, or is it maintained only by the upstream Linux community?
    5. Are any additional TI-specific modifications required when using this driver with an NXP i.MX8M Plus BSP?

    3. External DisplayPort and DP Alt Mode connection

    The SN65DSI86 is described as a MIPI DSI-to-eDP bridge. In our application, its DP output may be connected to an external DP sink through the TUSB546A and a USB Type-C DP Alt Mode path.

    From the SN65DSI86 perspective, are there any restrictions or concerns regarding the following operations?

    • HPD propagation from the external DP sink
    • EDID reading through AUX
    • Hot-plug and reconnection
    • DP link training after cable connection
    • Operation through the TUSB546A signal path

    The HPD interrupts can also be set for HPD_REGPLU, HPD_REMOVAL_EN and HPD_INSERTION_EN on register 0xE6, and the status of the HPD can be read from 0xF5 register as shown below.




    For using with the TUSB and USB-C, we would suggest to start a thread with the team supporting the TUSB parts so that you can get detailed responses about it.

    The DSI86 part itself, once it detects HPD and link training is start, the link training process can be done with manual, fast or semi-auto link trianing. The initialization sequence in the datasheet shows the steps for link training and also for reading EDID over AUX.

    For reading EDID, you can use these steps for the direct method mentioned in the datasheet: SN65DSI86: I2C over aux direct method


    Best regards,
    Ikram