DS90CR287 Levels

Hi Zach,

Welcome to LVDS! Here are links to some great reference materials:

- Channel Link Design Guide 

- LVDS Owner's Manual 

These references materials explain how LVDS works and also provide guidance for good pcb design. Both the + and - lines on an LVDS differential pari should have a around +1.2 V DC offset. This parameter ca vary somewhat, since true LVDS receiver should accept a wide input common mode range. Since you mentioned you are new to LVDS, be sure that you have the + line on the CR287 connected to the +line on your frame grabber's LVDS inputs, likewise the - line on the CR287 drivers should be connected to the - line on the frame grabber's LVDS inputs.

Now for your questions regarding the DS90CR287:

• Yes, PLLVCC, LVDSVCC and VCC all need to be tied to 3.3V. Though each pin should have its own bypass capacitors for power supply filtering. Be sure to have a bulk capacitor on PLLVCC
• All the ground planes should be tied together.
• Yes, the power down pin should be read as power down bar. Meaning the device will be powered down when the pin is pulled to logic LOW.

Hi Mike,

Thanks for the reply. Our differential pairs have the 1.2V offset, but it seems like there is too much noise in the signals to properly decode on the FG side. Its hard get decent measurements, as it is buried inside of a computer box, but it looks like its not able to get any logic off the LVDS signals. 

You said:  Yes, PLLVCC, LVDSVCC and VCC all need to be tied to 3.3V. Though each pin should have its own bypass capacitors for power supply filtering. Be sure to have a bulk capacitor on PLLVCC

The datasheet for the part was initially confusing, and we didn't realize we would need decoupling on the PLLVCC and LVDSVCC lines. Will the same decoupling scheme specified for the regular VCC lines need to be applied to both of these supplied for proper operation?

To the extent that we can probe on the FG side, we have followed your steps 1-3. Checking with other existing layouts and designs we can't see any discrepancies with our layout and integration with the chip. We have noticed that our bench-top power supplies are rather noisy. Specifically, the noise seems to be at the frequency of our clock source. Everything else to work fine on the board, except for the DS90CR287. Could the noisy sources be the cause of this?

Thanks again!

Zach

Hi Zach,

Power supply noise could certainly be a possible root cause. You should also consider input clock jitter and high speed signal integrity. Here is the user guide to the old evaluation kit, CLINK3V28BT-85:

3566.clink3v28bit85_final_rev2_1.pdf

This user guide has some good information and examples of what your waveforms should look like.

Another thing to consider would be the LVDS clock and data timing relationship, or how much skew is there between your clock and data? If you do not have a tightly phase controlled interconnect/cable then you may have a timing issue with the LVDS clock and data.

So what to do? Check the following:

- You must find a way to probe the LVDS signals. You will need to know if the signals going into the frame grabber are good or not. To do this you must probe across the 100 ohm differential terminations on the frame grabber board or at the device pins if the termination is integrated on chip.

- Next, look at the timing relationship between the LVDS clock and data. To do this you will need to be able to probe the LVDS clock and data at the same time.

- Then look at the quality of the LVCMOS input signals. You want to make sure there is no "undershoot" or excursion below the ground plane.

- Probe the input clock and observe the clock jitter.

-Probe the power supplies and measure the peak to peak noise observed. 

Mike Wolfe

DPS APPS / SVA

Hi Zach,

I haven't seen your system and i am thinking out loud here but if it is hard to get to the FG, how about if you terminate CR287 output one at a time and use scope probe to check the eye and etc? Your scope probe could be 100 Ohm diff and you may not need to add terminating R but try to AC couple.  It is preferable if we can do this measurement on the FG side but short of that we can do this measurement on the CR287 side. This will tell us if the CR287 data and clock outputs are decent. Also, you can check phase relation between the output clock and Tx lines.

Regards,,nasser