DP83867IS: Method for preventing packet loss when IFG<12Bytes

Hi Nishie-san,

It is interesting that the packet loss becomes worse when the register setting is switched from 0x4 to 0x3. Can you please share the packet loss figures you are seeing with 0x5, 0x4, and 0x3 register settings? Is it also possible to try testing with a higher IPG?

Best regards,

Greg

Hi Greg-san,

Thank you for your support.

Gregory Kobyakov said:

Can you please share the packet loss figures you are seeing with 0x5, 0x4, and 0x3 register settings?

Packet loss values for each setting

0x5: 50 packets in 1 second

0x4:1 packet in 12 hours

0x3:1 packet in 10 minutes

The test configuration is as follows.

Tester → SW where packet loss occurs → equipment with DP83867IS mounted

Tester continuously transmits Ethernet packets with IPG=12Byte and packet length =1400Byte

→ approx. 88526 packets/s, equivalent to approx. 990Mbps

Gregory Kobyakov said:

Is it also possible to try testing with a higher IPG?

Tested only when 0x5. In the above test system, it has been confirmed that packet loss occurs within a few minutes up to IPG=23Byte.

→ The higher the IPG, the lower the frequency.

Although it has not been confirmed for a long time, the frequency of loss occurs for several tens of minutes from around 25Byte.

Best Regards,

Nishie

Hello Nishie,

I am stepping in for Greg while he is traveling for the week.

At setting 0x3 for Viterbi register, can you please restart the PHY (Reg 0x1F[14] = '1') and once error is reported, please read Reg 0x15 and 0xA?

Sincerely,
Gerome

Hi Gerome-san,

Thank you for your support.

I will confirm my question with my customer.

Also, could you please tell me about the following that I originally asked? I would like to improve the behavior when set to 0x3, but I also want to know the validity of each setting.

1.Could you tell me how the internal behavior of PHY changes depending on the setting value (0x5/0x4/0x3) of VTM_CFG (address 0x 0053)?

2.Could you tell me the conditions and cases where using 0x3 is recommended?

Best Regards,

Nishie

Hello Nishie,

Please refer to section 3.5 of SNLA246 for information on the behavior of this device. If link partners send data with IPG < 12byte, this setting can be used to account for this behavior.

Sincerely,

Gerome

Hi Gerome-san,

Thank you for your reply.

1. I understand that you adjust the Viterbi threshold in DP83867, but could you tell me what the threshold is for each set value (0x5/0x4/0x3)?

2. When IPG<12, I can choose between 0x4 and 0x3, but I didn't understand the difference between them.

Best Regards,

Nishie

Hi Nishie-san,

Thank you for your reply.

It is difficult to provide the exact threshold as measuring direct IPG is a tricky task. However, we have seen IPGs down to 10 supported with value 0x3 anecdotally. I would recommend starting with this value in your prototyping and see if this addresses the packet errors seen at idle.

Sincerely,

Gerome

Hi Gerome-san,

Thank you for your support.

I would like to better understand the practical difference between VTM_CFG = 0x4 and VTM_CFG = 0x3. From your explanation, I understand that both settings are intended for short IFG/IPG conditions, and that 0x3 supports shorter IPG values than 0x4. Could you please provide more details on the following points?

1. What is the fundamental difference in PHY behavior between VTM_CFG = 0x4 and 0x3?

For example, how are the Viterbi threshold, receiver sensitivity, BER performance, and link margin affected?

2. What criteria should be used when selecting between 0x4 and 0x3?

Is the selection based only on IPG length, or are there other factors such as cable length, insertion loss, channel quality, packet size, or traffic pattern?

3. Are there any known scenarios where 0x4 can perform better than 0x3, even when the IPG is shorter than 12 bytes?

Best Regards,

Nishie

Hi Nishie-san,

Thank you for your query.

You may set Viterbi threshold to 0x3 or 0x4 to address low IPG being sent from link partner side. Think of this setting as a timer on byte for IPG when comparing setting values between 0x3-0x5. There are no known scenarios where 0x4 performs better than 0x3. Feel free to set this in prototyping and validate accordingly.

Sincerely,

Gerome

Hi Gerome-san,

Sorry for the late reply.

Gerome Cacho said:

At setting 0x3 for Viterbi register, can you please restart the PHY (Reg 0x1F[14] = '1') and once error is reported, please read Reg 0x15 and 0xA?

The result is as follows.

  -ieee-phy: reg:0x15 val:0x0003

  -ieee-phy: reg:0x0a val:0x3800

Best Regards,

Nishie

Hi Nishie-san,

I will provide further comments early next week.

Best regards,

Greg

Hi Greg-san,

Hi Nishie-san,

Apologies for the delay. I will provide an answer tomorrow.

Best regards,

Greg

Hi Nishie-san,

From the register reads, looks like the PHY operation is configured as normal and the RX error counter reads a value of 3. Can you please share the same reads for a VTM_CFG of 0x4?

Best regards,

Greg

Hi Greg-san,

ieee-phy: reg:0x15 val:0x0001
ieee-phy: reg:0x0a val:0x3800

Hi Greg-san,

Hi Greg-san,

Could you please let us know if there have been any updates?

Best Regards,

Nishie

Hi Nishie-san,

Apologies for the delay. Could you please clarify again if you are seeing packet loss issues with 0x04 VTM_CFG setting? Or are you more interesting in the functionality and details about this setting.

Best regards,

Greg

Hi Greg-san,

Hi Nishie-san,

What IPG is being used for this testing? Is it possible to check the high speed differential pairs with an oscilloscope to check if the signal reaches the full amplitude during high-frequency bursts?

Best regards,

Greg

Hi Greg-san,

Gregory Kobyakov said:

What IPG is being used for this testing?

Hi Nishie-san,

In general we have seen 0x03 setting work better than 0x04 for VTM_CFG for IPG<12 Bytes. However, this is not a strict rule. If the 0x04 setting works better, we advise using it for this application.

For the scope measurements, these should be sufficient conditions.

Best regards,

Greg

Hi,