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SN65DSI86-Q1: SN65DSI86-Q1 Schematic Review and Issue Check

CHEN Jimmy
Prodigy 20 points

Part Number: SN65DSI86-Q1

Hi TI Partner:

We need a schematics review of the DSI to DP bridge with the NXP iMX93 processor.

We want to implement the function of converting DSI signals to standard DP connector.

I have some question as following:

  1. DP AUX_N signal on connector side PU 100K to DP_PWR (3.3V) is correct or not? 
  2. When REFCLK is connected to X'tal, is it also possible to set DPPLL_CLK_SRC=1?

Thanks 

SN65DSI86-Q1 SCHEMATIC review.pdf 

  • 0
    TI__Mastermind 31580 points

    Hi Chen,

    Please give me 2-3 days to review and get back to you.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    TI__Mastermind 31580 points

    Hi Chen,

    Here is the feedback I had for the DSI86 schematic:

    • Please add at least one bulk (1uF or 10uF) capacitor to the the Vcc and Vcca 1.2V rails. Along with the smaller 100nF capacitors, bulk capacitor(s) will reduce noise over a greater frequency range
    • The DP Aux components used (resistor, capacitors, etc) will depend on whether you are using eDP or DP mode
      • For DP, the current schematic is okay.
        On the source side (DSI86) the DP_AUX_P is connected to ground with 100kOhm pulldown, and DP_AUX_N is connected to DP power 3.3V with 100kOhm pullup resistor
    • When REFCLK is used, the register settings can still be changed to use DSI input clock as source. However, note that if DSI clock is used, the clock rates must be continuous at specific frequencies listed in the datasheet register 0x0A.

    Let me know if you have any further questions.

    Best regards,
    Ikram