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TCA9517: TCA9517 side-B Bus Loading when is disable

andrea busi
Prodigy 10 points

Part Number: TCA9517

In the TCA 9517.png there is our schematic implementation.

MCU is able to reach successfully the AT24C256 EEprom, during the acces  the TCA9517 is disabled

 to avoid contention  .

We can see on SCL_RIM and SDA_RIM a "flat" on relative Rise edge ( see SDA_RIM_Rise and SCL_RIM_Rise). This is not present when TCA9517 is not mounted. Is there a possible explanation ? 

regard

Andrea Busi

Nokia Italy TCA9517.pngSCL_RIM_Rise (1).pngSDA_RIM_Rise.png

  • 0
    TI__Guru 65368 points

    Hi Andrea,

    We will respond soon. 

    Regards,

    Tyler

  • 0 in reply to Tyler Townsend
    TI__Guru 65368 points

    Hi Andrea,

    The voltage step looks to be ~800mV before rising to a VCC. 

    Do you have a complete schematic to share with us? I would like to review what is connected to each side of the buffer as well as the pull-up resistor selection for the device. 

    Also, the ATC24 device SDA/SCL driver is slightly weaker than the I2C spec. I.e. its ability to drive a logic low signal is VOL = 0.4V at 2.1mA IOL. The spec requires that all targets should be able to drive VOL = 0.4V at IOL = 3mA. 

    Regards,

    Tyler

  • 0
    Prodigy 10 points

    Hi Tyler,

    thanks for the Reply, I'm facing issue to upload a new file .

    Therefore

    MCU is a LATTICE lfe5u-25f-6bg256i

    Pull up 1K @ P3V3

    ATC vendors : 

    STM M24256-BRMN6

    ONSEMI CAT24C256WI

    9517 vendors:

    NXP  PCA9517ADP

    TI    TCA9517DGKR

    At the end we can see the flat on Rise time when TI is mounted only .

    No "Issue" with  either 2 flash vendors or NXP 9517

    I can confirm that we have never see failure on the bus with TI .

    But could be useful to understand this behavior 

    Br 

    Andrea

  • 0 in reply to andrea busi
    TI__Guru 65368 points

    Hi Andrea,

    Is it safe to say that the plateau is roughly 900mV to 1V? 

    Also, do you have a waveform of the rising edge on the NXP device? 

    I don't suspect that this voltage step will cause any issue because it looks monotonic. It wouldn't have risk to cause an i2c issue like a double clock edge.

    Regards,

    Tyler