Part Number: AM6442
Other Parts Discussed in Thread: TMDS64EVM, SYSCONFIG
I am facing issue with MCU SPI in peripheral mode.
AM6442 (AM64x family) (TMDS64EVM) MCU_M4FSS0_CORE0 (M4F)
Interface: MCU_SPI0 (clock phase and polarity mode 3), peripheral (slave) mode, 3-pin configuration, 8 bit data.
Connector: Safety J1
Pin 16 → MCU_SPI0_CLK (external clock input)
Pin 4 → MCU_SPI0_D0 (MISO output)
Pin 2 → MCU_SPI0_D1 (MOSI input)
Pin 23 → DGND (common ground)
I am proving external clock with common ground.
Problem:
TX transmits independently of clock, clock behaves as a chip-enable signal rather than clock: TX Data Not Synchronized with SPICLK.
Debugging:
M4F writes 0x99 (any data) to MCSPI_TX0 when CH0CTRL.EN=1
Data appears on MISO (D0) but does NOT shift synchronously with SPICLK edges
Byte appears to transmit regardless of clock timing
Clock Input Acts as Enable, Not Clock
External SPICLK transitions do not generate SPI bit shifts
TX transmission continues without clock gating
Data timing independent of SPICLK level
