Part Number: DP83867IR
Hi,
We are using the DP83867 in RGMII mode and have a question regarding the state of the RGMII output pins during hardware reset.
Our system configuration is:
- DP83867 powered and operating from valid supplies
- RESET_N actively held low
- Connected MAC/SoC is in power-up sequence
- During the SoC I/O power-up sequence, some GPIO/RGMII pins may temporarily glitch and drive High for a short duration
To evaluate the risk of output contention, we need to understand the exact drive state of the DP83867 pins while RESET_N is low.
Could you please clarify the state of the following pins when RESET_N = Low?
- RX_CLK
- RX_D0
- RX_D1
- RX_D2
- RX_D3
- RX_DV (RX_CTRL)
Specifically:
1. Are these pins tri-stated (Hi-Z) during RESET_N = Low?
2. Are any internal pull-up or pull-down structures enabled on these pins during reset?
3. Is there any possibility that the device actively drives High or Low on these outputs while RESET_N is asserted?
4. Is there any TI documentation that explicitly defines the pin state during hardware reset?
We found the power-up timing diagram showing:
"Latch-In of Hardware Configuration Pins" and
"Dual Function Pins Become Enabled As Outputs"
However, RX_CLK, RX_D1, and RX_D3 do not appear to be strap pins, so it is unclear whether these signals are guaranteed to remain Hi-Z while RESET_N is asserted.
Our goal is to determine whether holding RESET_N low is sufficient to prevent output contention between the DP83867 and a connected SoC during SoC power-up glitches.
Thank you.
