Part Number: TS3DV520E
Hi team,
I am using TS3DV520E to switch LVDS differential signals (5 pairs: 1 clock + 4 data)
for an LCD panel interface. The signal conditions are as follows:
- Resolution: XGA, 60 Hz
- Data rate: 500 Mbps per lane
Referring to the tsk(o) specification on the datasheet, which defines:
"Output skew between center port (A4 to A5) to any other port" = 0.1 ns max
I have the following three questions:
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Question 1: Skew between two non-center ports
Since tsk(o) is defined relative to the center port (A4/A5),
Could the skew between two non center ports (e.g., A0/A1 vs. A8/A9) be as large as 0.2 ns in the worst case?
Or is the skew guaranteed to be within 0.1 ns between any two arbitrary ports?
Question 2: Assigning LVDS clock to center port A4/A5
If I assign the LVDS clock signal to the center port (A4/A5),
is it correct to understand that the skew between the clock and all data ports is guaranteed to be within 0.1 ns?
The LCD panel has a strict specification on clock-to-data skew, so I would like to minimize
it as much as possible.
Question 3: Polarity of the skew specification
The tsk(o) value of 0.1 ns max does not include a ± sign.
Does this mean the skew is defined as a one-sided (positive only) value with respect to
the center port (A4/A5)?
Or should it be interpreted as ±0.1 ns (i.e., any other port could be either ahead of or
behind the center port by up to 0.1 ns)?
Best regards,
Goto
