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SN65DPHY440SS: HS mode to LP mode

user244678
Expert 1385 points

Part Number: SN65DPHY440SS
Other Parts Discussed in Thread: AWR2243,

We are considering using it to retime the CSI-2 output of the AWR2243.

Once the AWR2243 CSI-2 clock output begins operating in HS mode, it does not subsequently transition to LP mode.

If only the data lanes are in LP mode while the clock lane is in HS mode, will the SN65DPHY440SS operate in HS mode or LP mode?

And in this case, will the CSI2 clock output continue to oscillate in HS mode?

 

Best regards,

Hiroyuki Taguchi

  • +1
    TI__Guru**** 193041 points

    Taguchi-san

    The clock and data lane are separated from each other. 

    In this case, the clock will continue to oscillate in HS mode, but the data lane will transition between LP and HS mode, and data will only be sent during the HS mode.

    Please also note that in order to operate the clock in HS mode, you will have to configure the DPHY440 in I2C mode to disable the clock LP and enable HS mode only. 

    Below is the I2C write to enable clock lane in HS mode only.

    Write Register 0x50 with 8’h10 //Override enable for HS TX CLK path

    Write Register 0x51 with 8’h10 //HS TX CLK path enabled.

    Write Register 0x61 with 8’h00  // Disable LP path.

    Write Register 0x70 with 8’h10  //Override enable for HS RX CLK path

    Write Register 0x71 with 8’h10  // HS RX CLK path enabled.

    Please also note lane 0 is a special lane, if it is possible to not use lane 0 in the design, I would recommend not using it in the design.

    Thanks

    David