Part Number: SN65LVDS31
Other Parts Discussed in Thread: DS90LV048A,
Hello,
We need to model an SN65LVDS31 clock transmitter connected through PCB traces and board connectors to a DS90LV048A receiver.
Each differential pair connects to two input channels of the same receiver. There is one shared 100 ohm termination at the receiver end, not two parallel terminations.
BCLK is 12.288 MHz or 6.144 MHz. The intended supply range is 3.0 to 3.6 V and ambient temperature is -20 to +85 degrees C.
The SLLC012 download provides an SN65LVDS31D SOIC model with typical data and one rising and one falling waveform. The waveform fixtures use 50 ohms, 1.23 V and 10 pF. We need TSSOP package data and will not substitute SOIC package parasitics.
Please clarify:
1. What supported simulation or extraction method can use this single-waveform-per-edge, current-mode three-state model? Is a supported SPICE equivalent or another documented method available without HyperLynx? Our development environment is macOS. The open-source converters we examined require two waveform fixtures per edge.
2. Is a newer model available with minimum and maximum electrical data, additional waveform fixtures, and SN65LVDS31PW package data?
3. What load and input-transition conditions are necessary to apply the published transmitter and receiver propagation-delay limits when each differential pair connects to two receiver input channels?
4. How should we compare the DS90LV048A timing fixture's 0 to 100 percent input-transition requirement with simulated waveform results measured from 10 to 90 percent?
We need a supported model method and applicable timing conditions. We will keep typical simulation results separate from guaranteed voltage and temperature limits.
Kind regards,
Jonathan Reichardt
