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DS90UB953-Q1: DS90UB953ATRHBTQ1 : Part selection help

Udesh Singla
Intellectual 560 points

Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: DS90UB954-Q1

HI 

We are working on the ex-proof PTZ thermal camera design in which we are using the thermal moudle which is having the CMOS 16 Bit data output for thermal video and MIPI-4lane for radiometric data.

We need to travel these signals for upto 1m of distance from one barrel to another barrel.

Ex-Proof_Thermal_PTZ_Architecture_diagram-Page-23.drawio.png

We are following the below architecture to use the serializer IC.

Our camera moudle specs is as below:

Bit rate: 640x512

FPS: 30Hz

Ex-Proof_Thermal_PTZ_Architecture_diagram-Page-22.drawio (1).png

 

  • 0
    Intellectual 560 points

    Please check and let us know if we are using the correct part for our implementation.

    Let us know if you need more information

  • 0 in reply to Udesh Singla
    TI__Prodigy 690 points

    Hello Udesh,

    Thanks for the details. One important note on the DS90UB953-Q1 up front, then a few clarifying questions before we confirm the part selection.

    Important: DS90UB953-Q1 only accepts MIPI CSI-2 (D-PHY) input, it has no native 16-bit parallel/LVCMOS receiver. Your architecture already handles this correctly by using the FPGA to convert the CMOS 16-bit thermal video bus into CSI-2 before the serializer, so no change needed there. I just want to confirm this is intentional and not something you were hoping the 953 would do natively.

    To finish the review, could you confirm:

    1. What CSI-2 D-PHY TX IP is the FPGA using to output the converted thermal video (MIPI_DPHY0)? Is it a certified/compliant D-PHY v1.2 transmitter, or a soft/LVDS-based implementation? The 953's CSI-2 input must be DC-coupled to a true D-PHY-compliant source.
    2. How many CSI-2 data lanes and what line rate does the thermal module's radiometric MIPI output actually run at (per its datasheet)? Your diagram shows 4 lanes. I want to confirm the per-lane rate stays within 953's 832 Mbps/lane limit.
    3. Is the 640×512 @ 30Hz / 16-bit spec the same for both the thermal video path and the radiometric MIPI path, or do they differ in resolution/bit depth
    4. What CSI-2 data type is used for the 16-bit thermal video (RAW16, YUV422, or a proprietary long-packet type)?
    5. Which deserializer part number(s) are you pairing with each DS90UB953-Q1? Given your CV72 Ambarella takes native CSI-2 on MIPI_DCPHY and MIPI_CSI1, you'll want a CSI-2-output deserializer (e.g., DS90UB954-Q1) rather than a parallel-output variant.
    6. Do you plan to run Synchronous clocking mode (clock recovered from the deserializer back channel), or Non-Synchronous mode with a local reference clock at each serializer?
    7. Is the clock lane from the FPGA and from the thermal module continuous or non-continuous (gated)? This needs to match the 953's register 0x02[6] setting.
    8. Coax or shielded-twisted-pair (STP) for the ~1m run between barrels, and do you need Power-over-Coax/PoC on either link, or is power supplied locally at each end?

    Once I have these, I can confirm the full link budget and clocking configuration.

    Best regards,
    Caitlin Behne