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TL16C2550: CSA Control and INTA Interrupt Behavior During Transmit and Receive Operations

Hori Shota
Expert 1890 points

Part Number: TL16C2550

Hi team,
 
I have the following questions regarding the transmit and receive operations of the TL16C2550IPFB.
Transmit operation
  1. After starting data transmission from TXA, is it necessary to keep CSA Low until the transmission is complete?
  2. Is the CPU notified of transmission completion through an INTA interrupt?
Receive operation
  1. When data is received through TXA/RXA, is the CPU notified of reception completion through an INTA interrupt?
  2. Does this mean that the CPU does not need to continuously wait for incoming data and can read the receive buffer after the interrupt occurs?
Best Regards,
 Shota
  • +1
    TI__Expert 3300 points

    Hi Hori,

    Hori Shota said:
    After starting data transmission from TXA, is it necessary to keep CSA Low until the transmission is complete?

    No, due to the asynchronous nature of UART it does not need to be kept low until transmission is complete.

    Hori Shota said:
    Is the CPU notified of transmission completion through an INTA interrupt?

    Not exactly. One source of an INTA interrupt is "available transmit buffer space" which isn't exactly the same as transmission completion. You can get an interrupt for when the transmit FIO is empty (see the bottom of the datasheet page 24 for more)

    Hori Shota said:
    When data is received through TXA/RXA, is the CPU notified of reception completion through an INTA interrupt?

    Yes "available receiver data" is an explicit source for the INTA interrupt.

    Hori Shota said:
    Does this mean that the CPU does not need to continuously wait for incoming data and can read the receive buffer after the interrupt occurs?

    Correct

    -Ethan White