SN75LVDS83B: Rise time and Fall time requirement for Clock and Data

Part Number: SN75LVDS83B

Hello Team,

We are interfacing SN75LVDS83BDGGR with STM32N657 MCU. We have set highest drive strength ("Very High Speed") from MCU side. We are getting below rise time and fall time with clock and data signals. We are target display resoulation 1280 x 400 with 30fps. Later our plan to change to 60fps.

For Clock (10% to 90%)

As per requirement rise time : < 3ns and fall time : < 3ns

We are getting as per below 

1. Rise time : 3.024ns 

2. fall time : 3.845ns

For Data  (10% to 90%)

As per requirement rise time : < 3ns and fall time : < 3ns

We are getting as per below 

1. Rise time : 3.042ns

2. fall time : 3.903ns

 

Could you please guide us if this rise time and fall time will impact communication or not?

I have attached waveform for your reference.

Your quick response is highly appreciated.

LTDC_G4_FLATLINK_D9.png

 

LTDC_CLK.png

Thanks