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DP83620-EVK: Schematic Review

Bharath Kumar
Prodigy 40 points

Part Number: DP83620-EVK
Other Parts Discussed in Thread: DP83620

I want you're hardware expert to review our schematics  & provide us the feedback, sugesstions or recommendations.Ethernet Phi (DP83620) Schematics for TI IC Mfr Review.pdf 

  • +1
    TI__Mastermind 39045 points

    Hi Bharath,

    Please note DP83620 is an older device with support limited to existing documentation. That being said, here are my comments on the schematic:

    1. I see you are placing one PHY into address 0. Please note this will enable MII isolate mode if done through strapping. Make sure each PHY is strapped to a different address

    2. It may be helpful to add series resistor options on the MII lines between the MAC and the PHY (these can be 0 ohms). Series resistors provide a way to probe the signal and can be adjusted to slow the edge of MII signals if necessary. 

    3. Make sure the crystal Clock meets the specs in the PHY datasheet:

    4. I do not see the 50 ohm terminations on the MDI lines of the top PHY. Please make sure these have the correct terminations.

    5. Your LED implementation does not appear to follow the datasheet implementation. If an LED pin is strapped low, the pin will be active-high, and the LED should connect to GND. The opposite is true for a LED pin strapped high:

    In your case, you have a pulldown resistor on each LED pin, then route the LEDs up to VDD3V3 as though they are active-low. This is ok if you are choosing to either populate the pulldown or the LED connection, but both will not work at the same time.

    Best,

    Shane

  • 0
    Prodigy 40 points

    1. I added resistors for address selection. However, since the datasheet mentions internal weak pull-up and pull-down resistors, I am unsure if we should mark these external resistors as DNP (Do Not Populate) if they are not needed.

    2. We will check with signal integrity team an then ass if its necessary.

    3. OK, The crystal load capacitor value has been updated to 33 pF, based on calculation considering the crystal internal Load capacitance of 18pF & assuming PCB board stray capacitance of 3pf.

    4. We have now updated the schematics with 50 Ohms termination resistors and required capacitor for this circuit scheme.

    5. LED strapping has been updated with both pull-up and pull-down resistors, featuring a selectable mode. currently pull-down is depopulated as per our use case;

    6. Regarding the wiring configuration: this signal goes to to the cathode of LED but actual RJ45 (connector/magnetics) is placed another board at front side of our product,

        The anode side is already connected to the LED with a resistor to power supply.

  • 0 in reply to Bharath Kumar
    Prodigy 40 points

    DP83620 Schematics for IC Mfr TI Review_30th-OCT'26.pdf

    Attached here the updated schematics for your review & confirmation.

  • 0 in reply to Bharath Kumar
    TI__Mastermind 39045 points

    Hi Bharath,

    1. This looks good, the PHY will automatically strap into address 0001 based on the weak pull resistors internally.

    4. This looks good

    5/6. Understood. This looks correct for an active-low configuration (pullup resistor on LED pins, and LED cathode connection with anode to I/O voltage)

    Best,

    Shane