Part Number: AM67
Hello TI Team,
Is the AM67 EMMC/SDIO IO capable of drive strength control? I see that the J722S linux driver (link attached) has drive strength control capability, and has drive strength control registers within the public driver excel doc for the AM67. Could you confirm the AM67 has this capability?
https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j722s/09_02_00_05/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Storage/MMC-SD.html
Hello Nicolas,
Thank you for your query !
The MMC0 / eMMC does NOT have associated pad-configuration registers. The high-speed eMMCPHY connected to the MMC0 eMMC Host Controller has its own signal controls. For the eMMC-PHY hardware interface, output impedance control seems to be applied through the MMC_SSCFG_PHY_CTRL_1_REG[22:20] DR_TY bitfield.
For the MMC1 and MMC2 drive strength control is NOT possible from associated pad-config registers DRV_STR bitfield as it is implemented only for LVCMOS buffered pins and not for the MMC1 & MMC2 SDIO buffered pins.
I will need to cross check with the J722S / AM67 if the above eMMC drive strength control is applicable as well as if there are any knobs to enable changing drive strength at the MMC1/MMC2 pins.
Please expect that some delay may be possible depending on the availability / workload of the AM67 signal integrity / MMC experts.
Thank you for your patience !
Best Regards,
Anastas Yordanov
